Adjusted io types for communication between control unit and driver. Also started testbench
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src/control_socbridge_tb.vhd
Normal file
24
src/control_socbridge_tb.vhd
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@ -0,0 +1,24 @@
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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library work;
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use work.io_types.all;
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use work.socbridge_driver_tb_pkg.all;
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entity control_socbridge_tb is
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end entity control_socbridge_tb;
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architecture tb of control_socbridge_tb is
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begin
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clock_proc: process
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begin
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for i in 0 to 50 loop
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wait for cycle / 2;
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clock <= not clock;
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end loop;
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wait;
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end process clock_proc;
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end architecture tb;
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@ -7,9 +7,11 @@ use work.io_types.all;
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entity control_unit is
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port (
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clk, rst: in std_logic;
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control_in: in control_unit_in_t;
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control_out: out control_unit_out_t
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clk, rst : in std_logic;
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ext_control_in : in ext_control_unit_in_t;
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ext_control_out : out ext_control_unit_out_t;
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int_control_in : in int_control_unit_in_t;
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int_control_out : out int_control_unit_out_t;
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);
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end entity control_unit;
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@ -33,13 +35,13 @@ begin
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begin
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ored := '0';
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ready_reduction: for i in 0 to number_of_drivers - 1 loop
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ored := ored or control_in.active_driver(i);
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ored := ored or int_control_in.active_driver(i);
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end loop ready_reduction;
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control_out.driver_id <= state.curr_driver;
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control_out.address <= state.address;
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control_out.seq_mem_access_count <= state.seq_mem_access_count;
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control_out.ready <= state.ready;
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control_out.instruction <= state.instruction;
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int_control_out.driver_id <= state.curr_driver;
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int_control_out.address <= state.address;
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int_control_out.seq_mem_access_count <= state.seq_mem_access_count;
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int_control_out.ready <= state.ready;
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int_control_out.instruction <= state.instruction;
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end process comb_proc;
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sync_proc: process(clk, state)
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@ -54,10 +56,10 @@ begin
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else
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state.ready <= not ored;
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if ored = '0' then
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state.address <= control_in.address;
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state.seq_mem_access_count <= control_in.seq_mem_access_count;
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state.curr_driver <= control_in.driver_id;
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state.instruction <= control_in.instruction;
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state.address <= ext_control_in.address;
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state.seq_mem_access_count <= ext_control_in.seq_mem_access_count;
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state.curr_driver <= ext_control_in.driver_id;
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state.instruction <= ext_control_in.instruction;
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end if;
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end if;
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end if;
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@ -3,6 +3,12 @@ use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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package io_types is
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--- CONSTANTS ---
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constant number_of_drivers: natural := 3;
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constant address_width: natural := 32;
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constant seq_vector_length: natural := 8;
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constant inst_word_width: natural := 8;
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--- STANDARD TYPES ---
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type ext_protocol_def_t is record
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@ -15,25 +21,28 @@ package io_types is
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socbridge: ext_protocol_def_t;
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end record interface_inst_t;
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constant number_of_drivers: natural := 3;
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constant address_width: natural := 32;
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constant seq_vector_length: natural := 8;
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constant inst_word_width: natural := 8;
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type control_unit_out_t is record
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type ext_control_unit_in_t is record
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driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
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address: std_logic_vector(address_width - 1 downto 0);
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seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
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ready: std_logic;
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instruction: std_logic_vector(inst_word_width - 1 downto 0);
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end record control_unit_out_t;
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type control_unit_in_t is record
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driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
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address: std_logic_vector(address_width - 1 downto 0);
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seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
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instruction: std_logic_vector(inst_word_width - 1 downto 0);
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end record control_unit_in_t;
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type ext_control_unit_out_t is record
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ready: std_logic;
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end record ext_control_unit_out_t;
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type int_control_unit_out_t is record
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driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
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address: std_logic_vector(address_width - 1 downto 0);
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seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
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instruction: std_logic_vector(inst_word_width - 1 downto 0);
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end record control_unit_out_t;
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type int_control_unit_in_t is record
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active_driver: std_logic_vector(number_of_drivers - 1 downto 0)
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end record int_control_unit_out_t;
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--- PROTOCOL INFORMATION ---
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constant interface_inst : interface_inst_t := (
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socbridge => ("SoCBridge ", 8, 2, 2)
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@ -41,23 +50,23 @@ package io_types is
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--- AUTOGENERATED TYPES ---
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type ext_socbridge_in_t is record
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
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end record ext_socbridge_in_t;
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type ext_socbridge_out_t is record
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
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end record ext_socbridge_out_t;
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type int_socbridge_in_t is record
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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write_enable_in, is_full_out : std_logic;
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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write_enable_in, is_full_out : std_logic;
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end record int_socbridge_in_t;
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type int_socbridge_out_t is record
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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write_enable_out, is_full_in : std_logic;
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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write_enable_out, is_full_in : std_logic;
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end record int_socbridge_out_t;
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type ext_interface_in_t is record
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