added initial multi in-flight packets attempt, limited by receiving socbridge
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0eef36028a
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1be1f1bc63
@ -104,7 +104,11 @@ begin
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--- ### TX NEXT STATE ASSIGNMENTS ### ---
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case st.curr_tx_state is
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when IDLE =>
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if local_next_tx_transaction /= NO_OP then
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if (local_next_tx_transaction = WRITE or local_next_tx_transaction = WRITE_ADD) and not st.write_in_flight then
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next_tx_state <= TX_HEADER;
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elsif (local_next_tx_transaction = READ or local_next_tx_transaction = READ_ADD) and not st.read_in_flight then
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next_tx_state <= TX_HEADER;
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elsif local_next_tx_transaction = READ_RESPONSE or local_next_tx_transaction = WRITE_ACK then
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next_tx_state <= TX_HEADER;
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else
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next_tx_state <= IDLE;
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@ -116,7 +120,7 @@ begin
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elsif st.curr_tx_transaction = WRITE then
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next_tx_state <= TX_W_BODY;
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elsif st.curr_tx_transaction = READ then
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next_tx_state <= TX_AWAIT;
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next_tx_state <= IDLE;
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-- Responses
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elsif st.curr_tx_transaction = READ_RESPONSE then
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next_tx_state <= TX_R_BODY;
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@ -137,7 +141,7 @@ begin
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next_tx_state <= ADDR4;
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when ADDR4 =>
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if st.curr_tx_transaction = READ_ADD then
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next_tx_state <= TX_AWAIT;
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next_tx_state <= IDLE;
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elsif st.curr_tx_transaction = WRITE_ADD then
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next_tx_state <= TX_W_BODY;
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else
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@ -145,7 +149,7 @@ begin
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end if;
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when TX_W_BODY =>
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if st.tx_stage <= 1 then
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next_tx_state <= TX_AWAIT;
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next_tx_state <= IDLE;
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else
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next_tx_state <= TX_W_BODY;
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end if;
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@ -185,7 +189,11 @@ begin
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end if;
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when RX_R_BODY =>
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if st.rx_stage <= 1 then
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next_rx_state <= IDLE;
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if local_next_rx_transaction /= NO_OP then
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next_rx_state <= RX_HEADER;
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else
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next_rx_state <= IDLE;
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end if;
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else
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next_rx_state <= RX_R_BODY;
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end if;
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@ -311,12 +319,12 @@ begin
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trans_write_next_state <= AWAIT;
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-- Wait for driver to finish current instruction, then reenter SEND
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when AWAIT =>
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if trans_st.write.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then
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if trans_st.write.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and not st.write_in_flight then
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trans_write_next_state <= IDLE;
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elsif ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1'
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and st.curr_tx_state = IDLE then
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and not st.write_in_flight then
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trans_write_next_state <= IDLE;
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elsif st.curr_tx_state = IDLE and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE
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elsif not st.write_in_flight and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE
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or ip_to_socbridge_driver.flush = '1') then
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trans_write_next_state <= SEND;
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else
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@ -348,11 +356,11 @@ begin
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trans_read_next_state <= AWAIT;
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-- Wait for driver to finish current instruction, then reenter SEND
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when AWAIT =>
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if trans_st.read.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then
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if trans_st.read.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and not st.read_in_flight then
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trans_read_next_state <= IDLE;
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elsif ip_to_socbridge_driver.flush = '1'and st.curr_tx_state = IDLE then
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elsif ip_to_socbridge_driver.flush = '1'and not st.read_in_flight then
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trans_read_next_state <= IDLE;
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elsif st.curr_tx_state = IDLE then
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elsif not st.read_in_flight then
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trans_read_next_state <= SEND;
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else
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trans_read_next_state <= AWAIT;
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@ -369,7 +377,8 @@ begin
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next_tx_data_size <= st.rx_data_size;
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local_next_tx_transaction := READ_RESPONSE;
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end if;
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elsif trans_st.read.curr_state = SEND then
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elsif trans_st.read.curr_state = SEND
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and not ((st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD) and trans_st.write.curr_state = SEND) then
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if trans_st.read.is_first_word = '1' then
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local_next_tx_transaction := READ_ADD;
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else
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@ -423,6 +432,9 @@ begin
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st.curr_write_data <= (others => '0');
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st.curr_read_data <= (others => '0');
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socbridge_driver_to_ip.data <= (others => '0');
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st.read_in_flight <= false;
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st.write_in_flight <= false;
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st.last_sent_transaction <= NO_OP;
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valid_out <= '0';
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elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
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@ -437,8 +449,22 @@ begin
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valid_out <= '0';
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case st.curr_tx_state is
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when IDLE =>
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st.curr_tx_transaction <= next_tx_transaction;
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st.tx_data_size <= next_tx_data_size;
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if ip_to_socbridge_driver.flush = '1' then
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st.last_sent_transaction <= NO_OP;
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end if;
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if (next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD
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or next_tx_transaction = READ or next_tx_transaction = READ_ADD) then
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if not st.read_in_flight or not st.write_in_flight then
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st.curr_tx_transaction <= next_tx_transaction;
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st.tx_data_size <= next_tx_data_size;
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else
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st.curr_tx_transaction <= NO_OP;
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st.tx_data_size <= 0;
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end if;
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else
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st.curr_tx_transaction <= next_tx_transaction;
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st.tx_data_size <= next_tx_data_size;
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end if;
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if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE
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or next_tx_transaction = READ_RESPONSE then
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st.curr_tx_addr <= trans_st.write.curr_inst.address;
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@ -447,6 +473,18 @@ begin
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st.curr_tx_addr <= trans_st.read.curr_inst.address;
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st.tx_stage <= 0;
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end if;
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when TX_HEADER =>
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if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then
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st.last_sent_transaction <= st.curr_tx_transaction;
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if not (st.curr_rx_state = RX_HEADER and st.curr_rx_transaction = WRITE_ACK) then
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st.write_in_flight <= true;
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end if;
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elsif st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD then
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st.last_sent_transaction <= st.curr_tx_transaction;
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if not (st.curr_rx_state = RX_HEADER and st.curr_rx_transaction = READ_RESPONSE) then
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st.read_in_flight <= true;
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end if;
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end if;
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when TX_W_BODY =>
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if st.tx_stage > 0 then
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st.tx_stage <= st.tx_stage - 1;
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@ -468,12 +506,31 @@ begin
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st.rx_stage <= 0;
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end if;
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when RX_HEADER =>
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if st.curr_rx_transaction = WRITE_ACK then
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if not (st.curr_tx_state = TX_HEADER and (st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD)) then
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st.write_in_flight <= false;
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end if;
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elsif st.curr_rx_transaction = READ_RESPONSE then
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if not (st.curr_tx_state = TX_HEADER and (st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD)) then
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st.read_in_flight <= false;
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end if;
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end if;
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when RX_R_BODY =>
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valid_out <= '1';
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socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
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if st.rx_stage > 0 then
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st.rx_stage <= st.rx_stage - 1;
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end if;
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if next_rx_transaction /= NO_OP and st.rx_stage <= 1 then
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st.curr_rx_transaction <= next_rx_transaction;
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st.rx_data_size <= next_rx_data_size;
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if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
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or next_rx_transaction = READ_RESPONSE then
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st.rx_stage <= next_rx_data_size;
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else
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st.rx_stage <= 0;
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end if;
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end if;
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when RX_W_BODY =>
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if st.rx_stage > 0 then
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st.rx_stage <= st.rx_stage - 1;
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@ -8,6 +8,7 @@ use gan_ganimede.io_types.all;
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package socbridge_driver_pkg is
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subtype command_size_t is integer range 0 to 128;
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constant MAX_IN_FLIGHT : integer := 1;
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type transaction_t is
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(NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR, WRITE_ACK, READ_RESPONSE);
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@ -52,6 +53,9 @@ package socbridge_driver_pkg is
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curr_tx_addr : std_logic_vector(31 downto 0);
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curr_rx_read_addr : std_logic_vector(31 downto 0);
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curr_rx_write_addr : std_logic_vector(31 downto 0);
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read_in_flight : boolean;
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write_in_flight : boolean;
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last_sent_transaction : transaction_t;
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end record state_rec_t;
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impure function calc_parity(
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d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)
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