From 3fe4b9ceddbd3a1ea3f95c9065f44e2b9e70200d Mon Sep 17 00:00:00 2001 From: Adam Date: Tue, 8 Apr 2025 14:33:01 +0200 Subject: [PATCH] Fixed some bugs and made manager compatible with byte addressing --- src/manager/management_unit.vhd | 21 +++++++++++----- src/manager/management_unit_pkg.vhd | 4 ++- src/manager/management_unit_tb.vhd | 38 +++++++++++++++++------------ 3 files changed, 40 insertions(+), 23 deletions(-) diff --git a/src/manager/management_unit.vhd b/src/manager/management_unit.vhd index 747f49d..49df662 100644 --- a/src/manager/management_unit.vhd +++ b/src/manager/management_unit.vhd @@ -23,19 +23,28 @@ architecture rtl of management_unit is signal write_address : manager_word_t; signal read_address : manager_word_t; signal msg_size : manager_word_t; + -- Address indexing whole words, not bytes + signal word_address : natural; begin - -read_address <= manager_state.memory(to_integer(unsigned(read_address_index))); -write_address <= manager_state.memory(to_integer(unsigned(write_address_index))); + +word_address <= to_integer(shift_right(unsigned(socbridge_driver_to_manager.address), address_shift)); +read_address <= manager_state.memory(word_address); +write_address <= manager_state.memory(word_address); comb_proc: process(controller_to_manager, socbridge_driver_to_manager) begin -- Read data from manager to SoCBridge driver - manager_to_socbridge_driver.data <= manager_state.memory(to_integer(unsigned(socbridge_driver_to_manager.address))); + manager_to_socbridge_driver.ready <= '1'; + manager_to_socbridge_driver.data <= manager_state.memory(word_address); manager_to_socbridge_driver.valid <= '1'; end process comb_proc; +-- tre sorters sätt att avsluta en skrivning: +-- timeout om vi villha det +-- en lastbit genooom axi interface +-- vi har fått all data vi begärde. + seq_proc: process(clk) begin if rising_edge(clk) then @@ -44,7 +53,7 @@ begin else -- Write data from SoCBridge driver to address if socbridge_driver_to_manager.valid = '1' then - manager_state.memory(to_integer(unsigned(socbridge_driver_to_manager.address))) <= socbridge_driver_to_manager.data; + manager_state.memory(word_address) <= socbridge_driver_to_manager.data; if socbridge_driver_to_manager.address = read_address_index or socbridge_driver_to_manager.address = write_address_index then -- CLEAR BUFFER TO IP CORE @@ -60,7 +69,7 @@ begin -- Is there a write instruction in memory elsif write_address /= empty_word and controller_to_manager.ready = '1' then manager_to_controller.address <= write_address; - manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present + manager_to_controller.driver_id <= "1"; -- Only supports one driver at present manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size)); manager_to_controller.cmd <= "01"; else diff --git a/src/manager/management_unit_pkg.vhd b/src/manager/management_unit_pkg.vhd index d35b905..1981d0e 100644 --- a/src/manager/management_unit_pkg.vhd +++ b/src/manager/management_unit_pkg.vhd @@ -6,6 +6,8 @@ use ganimede.io_types.all; package management_types is constant WORD_SIZE : natural := 32; + -- Amount to right shift addres to convert e.g 0x00000004 to 0x00000001 for 32-bit words + constant address_shift : natural := natural(FLOOR(LOG2(real(WORD_SIZE) / real(8)))); subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0); constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0'); constant mem_words : natural := 64; @@ -17,7 +19,7 @@ package management_types is -- Index in memory array where memory write address is kept. -- Write is active while it is not all zero. Mutex with read address constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000001"; - constant access_size : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000010"; + constant access_size : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000002"; -- Status register for debugging type manager_state_t is record diff --git a/src/manager/management_unit_tb.vhd b/src/manager/management_unit_tb.vhd index a27f52a..dd91dd2 100644 --- a/src/manager/management_unit_tb.vhd +++ b/src/manager/management_unit_tb.vhd @@ -65,53 +65,59 @@ begin wait for cycle; rst <= '0'; - wait for 5 * cycle; - - report "Testing write to 0x00000005\n"; + report "Testing write to 0x00000014"; socbridge_driver_to_manager.data <= x"FA0FA0FA"; - socbridge_driver_to_manager.address <= x"00000005"; + socbridge_driver_to_manager.address <= x"00000014"; socbridge_driver_to_manager.valid <= '1'; wait for cycle; socbridge_driver_to_manager.valid <= '0'; socbridge_driver_to_manager.data <= x"00000000"; - assert manager_to_socbridge_driver.data = x"FA0FA0FA" report "Write to address 0x00000005 failed! expected 0xFA0FA0FA but got " & to_string(manager_to_socbridge_driver.data) & "\n" severity error; + socbridge_driver_to_manager.address <= x"00000000"; + wait for halfcycle; + assert manager_to_socbridge_driver.data = x"FA0FA0FA" report "Write to address 0x00000005 failed! expected 0xFA0FA0FA but got " & natural'image(to_integer(unsigned(manager_to_socbridge_driver.data))) severity error; wait for 5 * cycle; - report "Testing submission of write instruction of 10 words to address 0x40000000\n"; + report "Testing submission of write instruction of 10 words to address 0x40000000"; + controller_to_manager.ready <= '1'; socbridge_driver_to_manager.data <= x"40000000"; - socbridge_driver_to_manager.address <= x"00000001"; + socbridge_driver_to_manager.address <= x"00000004"; socbridge_driver_to_manager.valid <= '1'; wait for cycle; socbridge_driver_to_manager.data <= x"0000000A"; - socbridge_driver_to_manager.address <= x"00000002"; + socbridge_driver_to_manager.address <= x"00000008"; + socbridge_driver_to_manager.address <= x"00000000"; socbridge_driver_to_manager.valid <= '1'; wait for cycle; socbridge_driver_to_manager.valid <= '0'; socbridge_driver_to_manager.data <= x"00000000"; + wait for cycle; controller_to_manager.ready <= '1'; - assert manager_to_controller.address = x"40000000" report "Controller got the wrong address! Expected 0x40000000 but got" & to_string(manager_to_controller.address) & "\n" severity error; - assert manager_to_controller.cmd = "10" report "Controller got the wrong command! Expected 0b10 but got " & to_string(manager_to_controller.cmd) & "\n" severity error; - assert manager_to_controller.seq_mem_access_count = 10 report "Controller got the wrong message size! expected 10 but got " & natural'image(manager_to_controller.seq_mem_access_count) & "\n" severity error; + wait for halfcycle; + assert manager_to_controller.address = x"40000000" report "Controller got the wrong address! Expected 0x40000000 but got " & to_string(manager_to_controller.address) severity error; + assert manager_to_controller.cmd = "10" report "Controller got the wrong command! Expected 0b10 but got " & to_string(manager_to_controller.cmd) severity error; + assert manager_to_controller.seq_mem_access_count = 10 report "Controller got the wrong message size! expected 10 but got " & natural'image(manager_to_controller.seq_mem_access_count) severity error; wait for 5 * cycle; controller_to_manager.ready <= '0'; - report "Testing submission of read instruction of 20 words from address 0x50000000\n"; + report "Testing submission of read instruction of 20 words from address 0x50000000"; socbridge_driver_to_manager.data <= x"50000000"; socbridge_driver_to_manager.address <= x"00000000"; socbridge_driver_to_manager.valid <= '1'; wait for cycle; socbridge_driver_to_manager.data <= x"00000014"; - socbridge_driver_to_manager.address <= x"00000002"; + socbridge_driver_to_manager.address <= x"00000008"; socbridge_driver_to_manager.valid <= '1'; wait for cycle; socbridge_driver_to_manager.valid <= '0'; + socbridge_driver_to_manager.address <= x"00000000"; socbridge_driver_to_manager.data <= x"00000000"; controller_to_manager.ready <= '1'; - assert manager_to_controller.address = x"50000000" report "Controller got the wrong address! Expected 0x50000000 but got" & to_string(manager_to_controller.address) & "\n" severity error; - assert manager_to_controller.cmd = "01" report "Controller got the wrong command! Expected 0b01 but got " & to_string(manager_to_controller.cmd) & "\n" severity error; - assert manager_to_controller.seq_mem_access_count = 20 report "Controller got the wrong message size! expected 20 but got " & natural'image(manager_to_controller.seq_mem_access_count) & "\n" severity error; + wait for halfcycle; + assert manager_to_controller.address = x"50000000" report "Controller got the wrong address! Expected 0x50000000 but got " & to_string(manager_to_controller.address) severity error; + assert manager_to_controller.cmd = "01" report "Controller got the wrong command! Expected 0b01 but got " & to_string(manager_to_controller.cmd) severity error; + assert manager_to_controller.seq_mem_access_count = 20 report "Controller got the wrong message size! expected 20 but got " & natural'image(manager_to_controller.seq_mem_access_count) severity error; wait; end process tb_proc;