From 44018d5827b7deb829de95b3c102056850e695ba Mon Sep 17 00:00:00 2001
From: Adam <admag2001@gmail.com>
Date: Thu, 10 Apr 2025 16:14:16 +0200
Subject: [PATCH] Started work on fifo buffer

---
 src/fifo_buffer/fifo_buffer.vhd | 50 +++++++++++++++++++++++++++++++++
 src/vhdl_ls.toml                |  3 ++
 2 files changed, 53 insertions(+)
 create mode 100644 src/fifo_buffer/fifo_buffer.vhd

diff --git a/src/fifo_buffer/fifo_buffer.vhd b/src/fifo_buffer/fifo_buffer.vhd
new file mode 100644
index 0000000..a38585d
--- /dev/null
+++ b/src/fifo_buffer/fifo_buffer.vhd
@@ -0,0 +1,50 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use ieee.numeric_std.all;
+library gan_ganimede;
+use gan_ganimede.io_types.all;
+library techmap;
+use techmap.gencomp.all;
+
+entity fifo_buffer is
+  generic (
+    data_width : natural := 32;
+    buffer_size : natural := 64
+  );
+  port (
+    ready_in : in std_logic;
+    ready_out : out std_logic;
+    valid_in : in std_logic;
+    valid_out : out std_logic;
+    data_in : in std_logic_vector(data_width - 1 downto 0);
+    data_out : out std_logic_vector(data_width - 1 downto 0)
+  );
+end entity fifo_buffer;
+
+architecture rtl of fifo_buffer is
+  signal read_pointer : natural range 0 to buffer_size - 1;
+  signal write_pointer : natural range 0 to buffer_size - 1;
+begin
+  
+  techmap_ram_inst : techmap.syncram_2p -- TODO figure out what all this means
+  generic map(tech => nx; abits : integer := 6; dbits : integer := 8;
+	sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
+	words : integer := 0; custombits : integer := 1;
+        pipeline : integer range 0 to 15 := 0; rdhold : integer := 0);
+  port map(
+    rclk     : in std_ulogic;
+    renable  : in std_ulogic;
+    raddress : in std_logic_vector((abits -1) downto 0);
+    dataout  : out std_logic_vector((dbits -1) downto 0);
+    wclk     : in std_ulogic;
+    write    : in std_ulogic;
+    waddress : in std_logic_vector((abits -1) downto 0);
+    datain   : in std_logic_vector((dbits -1) downto 0);
+    testin   : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none; 
+    customclk: in std_ulogic := '0';
+    customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
+    customout:out std_logic_vector(custombits-1 downto 0)
+    );
+  
+end architecture rtl;
diff --git a/src/vhdl_ls.toml b/src/vhdl_ls.toml
index 9a25589..d8238fc 100644
--- a/src/vhdl_ls.toml
+++ b/src/vhdl_ls.toml
@@ -16,6 +16,9 @@ gan_controller.files = [
 gan_manager.files = [
     'manager/*.vhd',
 ]
+gan_buffer.files = [
+    'fifo_buffer/*.vhd',
+]
 grlib.files = [
    'grlib-com-nx-2024.4-b4295/lib/grlib/**/*.vhd',
 ]