Standardized fifo types and names

src/fifo_buffer/fifo_buffer.vhd

@@ -9,7 +9,7 @@ use techmap.gencomp.all;
 
 entity fifo_buffer is
   generic (
-    data_width : natural := 32;
+    data_width : natural := 8;
     buffer_size : natural := 64;
     tech : integer := nx
   );

src/ganimede/ganimede.vhd

@@ -29,9 +29,6 @@ architecture rtl of ganimede_toplevel is
   signal manager_to_socbridge_driver : manager_to_socbridge_driver_t;
   signal socbridge_driver_to_buffer : socbridge_driver_to_ip_t;
   signal buffer_to_socbridge_driver : ip_to_socbridge_driver_t; --TODO determine where we want to declare the IP
-  signal dummy_ready : std_logic;
-  signal dummy_valid : std_logic;
-  signal dummy_data : std_logic_vector(31 downto 0);
 
   --signal gan_socbridge_WE_in : std_logic;
   --signal gan_socbridge_WE_out : std_logic;
@@ -80,24 +77,24 @@ begin
     port map(
       clk => clk, 
       rst => rst,
-      ready_in => dummy_ready,
+      ready_in => ip_to_ganimede.socbridge.ready,
-      ready_out => ip_to_ganimede.socbridge.is_full_in,
+      ready_out => buffer_to_socbridge_driver.ready,
-      valid_in => ganimede_to_ip.socbridge.write_enable_in,
+      valid_in => socbridge_driver_to_buffer.valid,
-      valid_out => dummy_valid,
+      valid_out => ganimede_to_ip.socbridge.valid,
-      data_in => ganimede_to_ip.socbridge.payload,
+      data_in => socbridge_driver_to_buffer.payload,
-      data_out => dummy_data
+      data_out => ganimede_to_ip.socbridge.payload
     );
 
   fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer
     port map(
       clk => clk, 
       rst => rst,
-      ready_in => ganimede_to_ip.socbridge.is_full_out,
+      ready_in => socbridge_driver_to_buffer.ready,
-      ready_out => dummy_ready,
+      ready_out => ganimede_to_ip.socbridge.ready,
-      valid_in => dummy_valid,
+      valid_in => ip_to_ganimede.socbridge.valid,
-      valid_out => ip_to_ganimede.socbridge.write_enable_out,
+      valid_out => buffer_to_socbridge_driver.valid,
-      data_in => dummy_data,
+      data_in => ip_to_ganimede.socbridge.payload,
-      data_out => ip_to_ganimede.socbridge.payload
+      data_out => buffer_to_socbridge_driver.payload
     );
   --- LATER WE ADD OPTIMIZATIONS HERE ---
 

src/ganimede/io_type_pkg.vhd

@@ -63,12 +63,12 @@ package io_types is
 
   type socbridge_driver_to_ip_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
-    write_enable_in, is_full_out : std_logic;
+    ready, valid : std_logic;
   end record socbridge_driver_to_ip_t;
 
   type ip_to_socbridge_driver_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
-    write_enable_out, is_full_in : std_logic;
+    ready, valid : std_logic;
   end record ip_to_socbridge_driver_t;
 
   type controller_to_drivers_t is record

src/socbridge/socbridge_driver.vhd

@@ -212,8 +212,8 @@ begin
 
   --- Combinatorial output based on current state ---
     local_next_data_out := (others => '0');
-    socbridge_driver_to_ip.is_full_out <= '1';
+    socbridge_driver_to_ip.ready <= '0';
-    socbridge_driver_to_ip.write_enable_in <= '0';
+    socbridge_driver_to_ip.valid <= '0';
     socbridge_driver_to_ip.payload <= (others => '0');
     --- ### TX_STATE BASED OUTPUT ### ---
     case st.curr_tx_state is
@@ -226,7 +226,7 @@ begin
         end if;
       when TX_W_BODY =>
         if st.tx_stage > 0 then
-          socbridge_driver_to_ip.is_full_out <= '0';
+          socbridge_driver_to_ip.ready <= '1';
           local_next_data_out := ip_to_socbridge_driver.payload;
         end if;
       when TX_R_BODY =>
@@ -253,7 +253,7 @@ begin
       when RX_W_BODY =>
       when RX_R_BODY =>
         socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
-        socbridge_driver_to_ip.write_enable_in <= '1';
+        socbridge_driver_to_ip.valid <= '1';
       when RX_AWAIT =>
         if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
           socbridge_driver_to_manager.data <= st.curr_write_data;

src/socbridge/socbridge_driver_tb.vhd

@@ -92,13 +92,13 @@ begin
   internal_stimulus: process
     variable count : integer := 1;
   begin
-    ip_to_socbridge_driver.is_full_in <= '0';
+    ip_to_socbridge_driver.ready <= '0';
-    ip_to_socbridge_driver.write_enable_out <= '0';
+    ip_to_socbridge_driver.valid <= '1';
     wait until rst = '0';
     -- stimulus goes here
 
     while not done loop
-      wait until (rising_edge(socbridge_driver_to_ext.control(1)) or falling_edge(socbridge_driver_to_ext.control(1))) and socbridge_driver_to_ip.is_full_out = '0';
+      wait until (rising_edge(socbridge_driver_to_ext.control(1)) or falling_edge(socbridge_driver_to_ext.control(1))) and socbridge_driver_to_ip.ready = '1';
       ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(count, 8));
       count := count + 1;
     end loop;