From 4c4d62554fe3b1fea5b9e0de9991c6d6d378fa40 Mon Sep 17 00:00:00 2001
From: Adam <admag2001@gmail.com>
Date: Mon, 3 Mar 2025 16:59:06 +0100
Subject: [PATCH] testbench works

---
 src/control_unit_tb.vhd | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/control_unit_tb.vhd b/src/control_unit_tb.vhd
index 2787f70..0f2ce51 100644
--- a/src/control_unit_tb.vhd
+++ b/src/control_unit_tb.vhd
@@ -27,8 +27,15 @@ architecture tb of control_unit_tb is
   shared variable word_counter: natural := 0;
 
 begin
- 
-  clock <= not clock after cycle / 2;
+  
+  clock_proc: process
+  begin
+  for i in 0 to 50 loop
+    wait for cycle / 2;
+    clock <= not clock;
+  end loop;
+  wait;
+  end process clock_proc;
 
   control_unit_inst: entity work.control_unit
     port map(
@@ -47,6 +54,8 @@ begin
   control_input.address <= x"F0F0F0F0";
   control_input.seq_mem_access_count <= "00000111";
   word_counter := 3;
+  wait for cycle;
+  current_driver <= "010";
   
   report "entering loop with word_counter" & integer'image(word_counter);
   for_loop: for i in word_counter - 1 downto 0 loop