added initial record type for instructions in management

src/manager/management_unit.vhd

@@ -22,10 +22,25 @@ architecture rtl of management_unit is
   signal manager_state : manager_state_t;
   signal write_address : manager_word_t;
   signal read_address  : manager_word_t;
-  signal msg_size      : manager_word_t;
   -- Address indexing whole words, not bytes
   signal word_address  : natural;
+
+  function pack(word: manager_word_t) return std_logic_vector is
   begin
+    return word.address & word.size & word.command & word.reserved;
+  end function;
+  function unpack(word: std_logic_vector) return manager_word_t is
+    variable val : manager_word_t;
+  begin
+    val.address := word(31 downto 10);
+    val.size := word(9 downto 6);
+    val.command := word(5 downto 3);
+    val.reserved := word(2 downto 0);
+    return val;
+  end function;
+
+begin
+
 
 read_address  <= manager_state.memory(0);
 write_address <= manager_state.memory(1);
@@ -37,7 +52,7 @@ begin
   local_word_address := to_integer(shift_right(unsigned(socbridge_driver_to_manager.address and address_mask), address_shift));
   -- Read data from manager to SoCBridge driver
   manager_to_socbridge_driver.ready <= '1';
-  manager_to_socbridge_driver.data <= manager_state.memory(local_word_address);
+  manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address));
   manager_to_socbridge_driver.valid <= '1';
   word_address  <= local_word_address;
 end process comb_proc;
@@ -55,7 +70,7 @@ begin
     else
       -- Write data from SoCBridge driver to address
       if socbridge_driver_to_manager.valid = '1' then
-        manager_state.memory(word_address) <= socbridge_driver_to_manager.data;
+        manager_state.memory(word_address) <= unpack(socbridge_driver_to_manager.data);
         if socbridge_driver_to_manager.address = read_address_index
         or socbridge_driver_to_manager.address = write_address_index then
           -- CLEAR BUFFER TO IP CORE
@@ -63,16 +78,16 @@ begin
       end if;
 
       -- Is there a read instruction in memory
-      if read_address /= empty_word and controller_to_manager.ready = '1' then
+      if pack(read_address) /= empty_word and controller_to_manager.ready = '1' then
-        manager_to_controller.address <= read_address;
+        manager_to_controller.address <= read_address.address & "0000000000";
         manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
-        manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size));
+        manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
         manager_to_controller.cmd <= "10";
       -- Is there a write instruction in memory
-      elsif write_address /= empty_word and controller_to_manager.ready = '1' then
+      elsif pack(write_address) /= empty_word and controller_to_manager.ready = '1' then
-        manager_to_controller.address <= write_address;
+        manager_to_controller.address <= write_address.address & "0000000000";
         manager_to_controller.driver_id <= "1"; -- Only supports one driver at present
-        manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size));
+        manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
         manager_to_controller.cmd <= "01";
       else
       -- No instruction present in memory, all zeroes to control unit

src/manager/management_unit_pkg.vhd

@@ -9,7 +9,12 @@ package management_types is
   constant WORD_SIZE : natural := 32;
   -- Amount to right shift addres to convert e.g 0x00000004 to 0x00000001 for 32-bit words
   constant address_shift : natural := natural(CEIL(LOG2(real(WORD_SIZE) / real(8))));
-  subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0);
+  type manager_word_t is record
+    address: std_logic_vector(21 downto 0);
+    size: std_logic_vector(3 downto 0);
+    command: std_logic_vector(2 downto 0);
+    reserved: std_logic_vector(WORD_SIZE - 1 - (22 + 4 + 3) downto 0);
+  end record manager_word_t;
   constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
   constant mem_words : natural := 64;
   constant address_mask : std_logic_vector(WORD_SIZE - 1 downto 0) := std_logic_vector(to_unsigned(mem_words - 1, 32));
@@ -21,7 +26,6 @@ package management_types is
   -- Index in memory array where memory write address is kept.
   -- Write is active while it is not all zero. Mutex with read address
   constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000001";
-  constant access_size         : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000002";
 
   -- Status register for debugging
   type manager_state_t is record
@@ -30,16 +34,22 @@ package management_types is
   end record manager_state_t;
 
   -- reset value of status register
-  constant manager_state_reset_val : manager_state_t := ((others => (others => '0')), x"00000000");
+  constant manager_word_reset_val : manager_word_t := (
+  address => (others =>'0'),
+  size => (others => '0'),
+  command => (others => '0'),
+  reserved => (others => '0') 
+);
+  constant manager_state_reset_val : manager_state_t := ((others => manager_word_reset_val), manager_word_reset_val);
 
   type socbridge_driver_to_manager_t is record
-    address : manager_word_t;
+    address : std_logic_vector(WORD_SIZE - 1 downto 0);
-    data : manager_word_t;
+    data : std_logic_vector(WORD_SIZE - 1 downto 0);
     valid: std_logic;
   end record socbridge_driver_to_manager_t;
 
   type manager_to_socbridge_driver_t is record
-    data : manager_word_t;
+    data : std_logic_vector(WORD_SIZE - 1 downto 0);
     valid : std_logic;
     ready : std_logic;
   end record manager_to_socbridge_driver_t;