diff --git a/src/socbridge_driver.vhd b/src/socbridge_driver.vhd
index e9fcb6a..c92981c 100644
--- a/src/socbridge_driver.vhd
+++ b/src/socbridge_driver.vhd
@@ -16,6 +16,26 @@ entity socbridge_driver is
 end entity socbridge_driver;
 
 architecture rtl of socbridge_driver is
+  type command_t is 
+    (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR);
+
+  type response_t is 
+    (NO_OP, WRITE_ACK, READ_RESPONSE);
+
+  type state_t is
+    (RESET, IDLE, TX_HEADER, TX_BODY, TX_ACK, RX_HEADER, RX_RESPONSE, RX_BODY);
+
+  type ext_protocol_t is record
+    data   : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+    clk    : std_logic;
+    parity : std_logic;
+  end record ext_protocol_t;
+
+  type state_rec_t is record
+    curr_state: state_t;
+    ext_in_reg, ext_out_reg : ext_protocol_t; 
+  end record state_rec_t;
+
   pure function calc_parity(
     d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)
   ) return std_logic is
@@ -28,34 +48,48 @@ architecture rtl of socbridge_driver is
     return not parity;
   end function;
   
-  signal ext_d_in, ext_d_out,ext_d_in_reg, ext_d_out_reg : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
-  signal ext_clk_in, ext_clk_out, ext_parity_in, ext_parity_out, ext_next_parity_out : std_logic;
+  pure function create_ext_protocol_from_io_type_in(
+    input : ext_socbridge_in_t
+  ) return ext_protocol_t is
+  variable val : ext_protocol_t;
+  begin
+    val.data := input.payload;
+    val.clk := input.control(1);
+    val.parity := input.control(0);
+    return val;
+  end function;
+  pure function create_io_type_out_from_ext_protocol(
+    input : ext_protocol_t
+  ) return ext_socbridge_out_t is
+  variable val : ext_socbridge_out_t;
+  begin
+    val.payload:= input.data;
+    val.control(1) := input.clk;
+    val.control(0) := input.parity;
+    return val;
+  end function;
+  
+  signal next_parity_out : std_logic;
 
 
-  type command_t is 
-    (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR);
 
-  type response_t is 
-    (NO_OP, WRITE_ACK, READ_RESPONSE);
-
-  type state_t is
-    (RESET, IDLE, TX_HEADER, TX_BODY, TX_ACK, RX_HEADER, RX_RESPONSE, RX_BODY);
-
-  signal curr_state, next_state : state_t;
+  signal ext_in_rec : ext_protocol_t;
+  signal ext_out_rec : ext_protocol_t;
+  signal next_state : state_t;
   signal curr_command : command_t;
   signal curr_command_bits : std_logic_vector(4 downto 0);
   signal curr_respoonse : response_t;
   signal curr_response_bits : std_logic_vector(4 downto 0);
+  signal st : state_rec_t;
 begin
-  comb_proc: process(ext_in, int_out, ext_d_out_reg, ext_clk_out, ext_parity_out, curr_state)
+  comb_proc: process(ext_in, int_out, st)
   begin
-    ext_next_parity_out <= calc_parity(int_out.payload);
-    ext_out.payload <= ext_d_out_reg;
-    ext_out.control <= ext_clk_out & ext_parity_out;
-    ext_d_in <= ext_in.payload;
-    ext_parity_in <= ext_in.control(0);
-    ext_clk_in <= ext_in.control(1);
-    curr_response_bits <= ext_d_in(7 downto 3);
+    ext_in_rec <= create_ext_protocol_from_io_type_in(ext_in);
+    ext_out <= create_io_type_out_from_ext_protocol(ext_out_rec);
+    next_parity_out <= calc_parity(int_out.payload);
+    ext_out.payload <= st.ext_out_reg.data;
+    ext_out.control <= st.ext_out_reg.clk & st.ext_out_reg.parity;
+    curr_response_bits <= ext_in_rec.data(7 downto 3);
     -- Create combinational bindings for command/response types
     with curr_command select
       curr_command_bits <= "00000" when NO_OP,
@@ -97,7 +131,8 @@ begin
 --       |           |              |                           
 --       +-----------+--------------+                 
 --                                                            
-    case curr_state is
+--- Next State Assignment --- 
+    case st.curr_state is
       when IDLE => 
         if curr_command = WRITE or curr_command = WRITE_ADD then
           next_state <= TX_HEADER;
@@ -142,21 +177,23 @@ begin
   
   end process comb_proc;
   -- Process updating internal registers based on primary clock
-  seq_proc: process(ext_clk_in, rst)
+  seq_proc: process(ext_in_rec.clk, rst)
   begin
     if(rst = '1') then
-      ext_d_in_reg <= (others => '0');
-      ext_d_out_reg <= (others => '0');
-      ext_clk_out <= '0';
-      ext_parity_out <= '1';
-      curr_state <= IDLE;
+      st.ext_in_reg.data <= (others => '0');
+      st.ext_out_reg.data <= (others => '0');
+      st.ext_out_reg.clk <= '0';
+      st.ext_out_reg.parity <= '1';
+      st.curr_state <= IDLE;
 
-    elsif(rising_edge(ext_clk_in)) then
-      ext_clk_out <= not ext_clk_out;
-      ext_d_in_reg <= ext_d_in;
-      ext_d_out_reg <= int_out.payload;
-      ext_parity_out <= ext_next_parity_out; 
-      curr_state <= next_state;
+    elsif(rising_edge(ext_in_rec.clk)) then
+      st.ext_in_reg.data <= ext_in_rec.data;
+      st.ext_in_reg.clk <= ext_in_rec.clk;
+      st.ext_in_reg.parity <= ext_in_rec.parity;
+      st.ext_out_reg.data <= int_out.payload;
+      st.ext_out_reg.clk <= not st.ext_out_reg.clk;
+      st.ext_out_reg.parity <= next_parity_out; 
+      st.curr_state <= next_state;
     end if; 
   end process seq_proc;