in progress of adding addressing for write command
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2149c1ec68
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547ff21a53
@ -11,6 +11,7 @@ entity socbridge_driver is
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clk : in std_logic;
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rst : in std_logic;
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cmd : in command_t;
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address : in std_logic_vector(31 downto 0);
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cmd_size: in positive;
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ext_in : in ext_socbridge_in_t;
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ext_out : out ext_socbridge_out_t;
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@ -26,8 +27,7 @@ architecture rtl of socbridge_driver is
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shared variable ext_out_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
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signal test : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
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signal next_state : state_t;
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signal curr_command : command_t;
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signal curr_command_bits : std_logic_vector(4 downto 0);
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signal curr_cmd_bits : std_logic_vector(4 downto 0);
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signal curr_response : response_t;
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signal curr_response_bits : std_logic_vector(4 downto 0);
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signal st : state_rec_t;
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@ -38,8 +38,7 @@ begin
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G_ext_in_rec <= ext_in_rec;
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G_next_state <= next_state;
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G_ext_out_data_cmd <=test;
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G_curr_command <= curr_command;
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G_curr_command_bits <= curr_command_bits;
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G_curr_command_bits <= curr_cmd_bits;
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G_curr_response <= curr_response;
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G_curr_response_bits <= curr_response_bits;
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G_st <= st;
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@ -81,19 +80,32 @@ begin
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--- State Transition Diagram ---
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--
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-- +-----+
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-- \|/ |
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-- RESET --+
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-- |
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-- |
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--
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--
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-- +-----+
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-- | |
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-- \|/ /--+
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-- IDLE<-------------------+
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-- / \ |
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-- / \ |
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-- / \ |
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-- \|/ \|/ |
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-- TX_HEADER RX_HEADER |
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-- | | |
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-- | | ----+ |
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-- |\ / | |
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-- | \ / | |
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-- | ADDR1 | |
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-- | | | |
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-- | \|/ | |
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-- | ADDR2 | |
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-- | | | |
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-- | \|/ | |
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-- | ADDR3 | |
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-- | | | |
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-- | \|/ | |
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-- | ADDR4 | |
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-- | /\ | |
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-- | / \ | |
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-- |-+ +----| +---+ |
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-- \|/ \|/ \|/ | |
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-- TX_BODY RX_RESPONSE---+ |
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-- | | |
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@ -114,8 +126,6 @@ begin
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else
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next_state <= IDLE;
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end if;
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when RESET =>
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next_state <= IDLE;
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when TX_HEADER =>
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-- The header only takes one word (cycle) to transmit.
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-- Continue to body directly afterwards.
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@ -150,6 +160,16 @@ begin
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-- Here we want to stay in RX_BODY for the duration of a packet.
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-- Right now, we receive only one single word at a time for simplicity
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next_state <= IDLE;
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when ADDR1 =>
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next_state <= ADDR2;
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when ADDR2 =>
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next_state <= ADDR3;
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when ADDR3 =>
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if st.cmd_reg = WRITE or st.cmd_reg = WRITE_ADD then
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next_state <= TX_BODY;
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else
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next_state <= RX_BODY;
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end if;
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end case;
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--- Combinatorial output based on current state ---
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@ -158,34 +178,27 @@ begin
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int_in.write_enable_in <= '0';
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case st.curr_state is
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when IDLE =>
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if cmd = WRITE or cmd = WRITE_ADD then
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curr_command <= cmd;
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ext_out_data_cmd := get_command_bits(cmd) & get_size_bits(cmd_size);
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elsif cmd = READ or cmd = READ_ADD then
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curr_command <= cmd;
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ext_out_data_cmd := get_command_bits(cmd) & get_size_bits(cmd_size);
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end if;
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when RESET =>
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when TX_HEADER =>
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if cmd = WRITE_ADD then
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--ext_out_data_cmd := address;
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else
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ext_out_data_cmd := int_out.payload;
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end if;
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int_in.is_full_out <= '0';
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when TX_BODY =>
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if curr_response = WRITE_ACK then
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ext_out_data_cmd := "00000000";
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if st.cmd_reg = WRITE_ADD then
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ext_out_data_cmd := st.addr_reg(7 downto 0);
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else
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ext_out_data_cmd := int_out.payload;
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int_in.is_full_out <= '0';
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end if;
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when TX_BODY =>
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ext_out_data_cmd := int_out.payload;
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int_in.is_full_out <= '0';
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when TX_ACK =>
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when RX_HEADER =>
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curr_command <= READ;
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ext_out_data_cmd := curr_command_bits & get_size_bits(cmd_size);
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ext_out_data_cmd := get_cmd_bits(st.cmd_reg) & get_size_bits(cmd_size);
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when RX_RESPONSE =>
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when RX_BODY =>
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when ADDR1 =>
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ext_out_data_cmd := st.addr_reg(15 downto 8);
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when ADDR2 =>
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ext_out_data_cmd := st.addr_reg(23 downto 16);
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when ADDR3 =>
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ext_out_data_cmd := st.addr_reg(31 downto 24);
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end case;
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next_parity_out <= calc_parity(ext_out_data_cmd);
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--- DEBUG GLOBAL BINDINGS ---
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@ -204,6 +217,8 @@ begin
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st.curr_state <= IDLE;
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st.write_stage <= 0;
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st.read_stage <= 0;
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st.cmd_reg <= NO_OP;
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st.addr_reg <= (others => '0');
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elsif(rising_edge(ext_in_rec.clk)) then
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st.ext_in_reg.data <= ext_in_rec.data;
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@ -214,21 +229,27 @@ begin
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st.ext_out_reg.parity <= next_parity_out;
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st.curr_state <= next_state;
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case st.curr_state is
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when IDLE =>
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if cmd = WRITE or cmd = WRITE_ADD or
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cmd = READ or cmd = READ_ADD then
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st.addr_reg <= address;
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st.cmd_reg <= cmd;
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end if;
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when TX_HEADER =>
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if curr_command = WRITE then
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if st.cmd_reg = WRITE then
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st.write_stage <= 2**(cmd_size - 1) - 1;
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elsif curr_command = WRITE_ADD then
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st.write_stage <= 2**(cmd_size - 1);
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elsif st.cmd_reg = WRITE_ADD then
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st.write_stage <= 2**(cmd_size - 1) + 3;
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end if;
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when TX_BODY =>
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if st.write_stage > 0 then
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st.write_stage <= st.write_stage - 1;
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end if;
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when RX_HEADER =>
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if curr_command = READ then
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if st.cmd_reg = READ then
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st.read_stage <= 2**(cmd_size - 1) - 1;
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elsif curr_command = WRITE_ADD then
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st.read_stage <= 2**(cmd_size - 1);
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elsif st.cmd_reg = READ_ADD then
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st.read_stage <= 2**(cmd_size - 1) + 3;
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end if;
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when RX_BODY =>
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if st.read_stage > 0 then
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@ -130,7 +130,7 @@ begin
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wait for CLK_PERIOD /4;
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check_next_state(TX_HEADER);
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wait for CLK_PERIOD * 3 / 4;
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expected_out <= get_command_bits(WRITE) & get_size_bits_sim(2);
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expected_out <= get_cmd_bits(WRITE) & get_size_bits_sim(2);
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check_next_state(TX_BODY);
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wait for CLK_PERIOD;
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expected_out <= "00000001";
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@ -16,7 +16,9 @@ package socbridge_driver_tb_pkg is
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(NO_OP, WRITE_ACK, READ_RESPONSE);
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type state_t is
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(RESET, IDLE, TX_HEADER, TX_BODY, TX_ACK, RX_HEADER, RX_RESPONSE, RX_BODY);
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(IDLE, ADDR1, ADDR2, ADDR3,
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TX_HEADER, TX_BODY, TX_ACK,
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RX_HEADER, RX_RESPONSE, RX_BODY);
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type ext_protocol_t is record
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data : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
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@ -28,6 +30,8 @@ package socbridge_driver_tb_pkg is
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curr_state: state_t;
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ext_in_reg, ext_out_reg : ext_protocol_t;
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write_stage, read_stage : NATURAL;
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cmd_reg : command_t;
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addr_reg : std_logic_vector(31 downto 0);
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end record state_rec_t;
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impure function calc_parity(
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d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)
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@ -36,7 +40,7 @@ package socbridge_driver_tb_pkg is
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input: ext_protocol_t
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) return ext_socbridge_out_t;
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function to_string ( a: std_logic_vector) return string;
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pure function get_command_bits(command : command_t) return std_logic_vector;
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pure function get_cmd_bits(command : command_t) return std_logic_vector;
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pure function get_size_bits(size : command_size_t) return std_logic_vector;
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pure function get_size_bits_sim(size : command_size_t) return std_logic_vector;
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--- DEBUG GLOBAL SIGNALS ---
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@ -88,7 +92,7 @@ package body socbridge_driver_tb_pkg is
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val.control(0) := input.parity;
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return val;
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end function;
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pure function get_command_bits(command : command_t)
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pure function get_cmd_bits(command : command_t)
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return std_logic_vector is
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variable val : std_logic_vector(4 downto 0);
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begin
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