From 554e3cadabeab4a04b1dd62d8c97d837b33e40c3 Mon Sep 17 00:00:00 2001 From: Adam Date: Tue, 15 Apr 2025 18:06:34 +0200 Subject: [PATCH] buffer probably done but untested, need to rework ganimede toplevel --- src/fifo_buffer/fifo_buffer.vhd | 116 ++++++++++++++++++++++----- src/ganimede/ganimede.vhd | 30 ++++++- src/gantry.toml | 137 +------------------------------- 3 files changed, 128 insertions(+), 155 deletions(-) diff --git a/src/fifo_buffer/fifo_buffer.vhd b/src/fifo_buffer/fifo_buffer.vhd index a38585d..daaeaf3 100644 --- a/src/fifo_buffer/fifo_buffer.vhd +++ b/src/fifo_buffer/fifo_buffer.vhd @@ -10,9 +10,11 @@ use techmap.gencomp.all; entity fifo_buffer is generic ( data_width : natural := 32; - buffer_size : natural := 64 + buffer_size : natural := 64; + tech : integer := nx ); port ( + clk, rst : in std_logic; ready_in : in std_logic; ready_out : out std_logic; valid_in : in std_logic; @@ -23,28 +25,100 @@ entity fifo_buffer is end entity fifo_buffer; architecture rtl of fifo_buffer is - signal read_pointer : natural range 0 to buffer_size - 1; - signal write_pointer : natural range 0 to buffer_size - 1; + constant address_bits : natural := integer(ceil(log2(real(buffer_size)))); + signal read_pointer : std_logic_vector(address_bits - 1 downto 0); + signal write_pointer : std_logic_vector(address_bits - 1 downto 0); + signal data_out_signal : std_logic_vector(data_width - 1 downto 0); + signal data_in_signal : std_logic_vector(data_width - 1 downto 0); + signal write_signal : std_logic; + signal buffer_full : std_logic; + signal buffer_empty : std_logic; + signal customout : std_logic_vector(0 downto 0); -- techmap needs customout and it is does not have a default value for some reason begin - - techmap_ram_inst : techmap.syncram_2p -- TODO figure out what all this means - generic map(tech => nx; abits : integer := 6; dbits : integer := 8; - sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0; - words : integer := 0; custombits : integer := 1; - pipeline : integer range 0 to 15 := 0; rdhold : integer := 0); + +-- DECLARATION OF NX_SYNCRAM +--entity nx_syncram_be is +-- generic ( abits : integer := 6; +-- dbits : integer := 8 +-- ); +-- port ( +-- clk : in std_ulogic; +-- address : in std_logic_vector (abits -1 downto 0); +-- datain : in std_logic_vector (dbits -1 downto 0); +-- dataout : out std_logic_vector (dbits -1 downto 0); +-- enable : in std_logic_vector (dbits/8-1 downto 0); +-- write : in std_logic_vector (dbits/8-1 downto 0) +-- ); +--end; + + techmap_ram_inst : entity techmap.syncram_2p + generic map(tech => tech, + abits => address_bits, + dbits => data_width + ) port map( - rclk : in std_ulogic; - renable : in std_ulogic; - raddress : in std_logic_vector((abits -1) downto 0); - dataout : out std_logic_vector((dbits -1) downto 0); - wclk : in std_ulogic; - write : in std_ulogic; - waddress : in std_logic_vector((abits -1) downto 0); - datain : in std_logic_vector((dbits -1) downto 0); - testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none; - customclk: in std_ulogic := '0'; - customin : in std_logic_vector(custombits-1 downto 0) := (others => '0'); - customout:out std_logic_vector(custombits-1 downto 0) + rclk => clk, + renable => '1', + raddress => read_pointer, + dataout => data_out_signal, + wclk => clk, + write => write_signal, + waddress => write_pointer, + datain => data_in_signal, + customclk => clk, + customout => customout ); + +comb_proc: process(write_pointer, read_pointer) + variable write_pointer_inc : unsigned(address_bits - 1 downto 0) := unsigned(write_pointer); +begin + ready_out <= '1'; + write_pointer_inc := unsigned(write_pointer) + 1; + customout <= "0"; + if write_pointer_inc = unsigned(read_pointer) then + buffer_full <= '1'; + else + buffer_full <= '0'; + end if; + + if write_pointer = read_pointer then + buffer_empty <= '1'; + else + buffer_empty <= '0'; + end if; +end process comb_proc; + +seq_proc: process(rst, clk) +begin + if rising_edge(clk) then + if rst = '1' then + ready_out <= '0'; + valid_out <= '0'; + read_pointer <= (others => '0'); + write_pointer <= (others => '0'); + data_in_signal <= (others => '0'); + data_out_signal <= (others => '0'); + write_signal <= '0'; + buffer_full <= '0'; + else + if ready_in = '1' and buffer_empty = '0' then + data_out <= data_out_signal; + valid_out <= '1'; + read_pointer <= std_logic_vector(unsigned(read_pointer) + 1); + else + valid_out <= '0'; + data_out <= (others => '0'); + end if; + if valid_in = '1' then + data_in_signal <= data_in; + write_signal <= '1'; + write_pointer <= std_logic_vector(unsigned(write_pointer) + 1); + else + write_signal <= '0'; + data_in_signal <= (others => '0'); + end if; + end if; + end if; +end process seq_proc; end architecture rtl; diff --git a/src/ganimede/ganimede.vhd b/src/ganimede/ganimede.vhd index a05f623..32fe9fa 100644 --- a/src/ganimede/ganimede.vhd +++ b/src/ganimede/ganimede.vhd @@ -7,6 +7,7 @@ use gan_socbridge.socbridge_driver_pkg.all; library gan_controller; library gan_manager; use gan_manager.management_types.all; +library gan_buffer; entity ganimede_toplevel is port ( @@ -26,7 +27,11 @@ architecture rtl of ganimede_toplevel is signal controller_to_manager : controller_to_manager_t; signal socbridge_driver_to_manager : socbridge_driver_to_manager_t; signal manager_to_socbridge_driver : manager_to_socbridge_driver_t; - + signal socbridge_driver_to_buffer : socbridge_driver_to_ip_t; + signal buffer_to_socbridge_driver : ip_to_socbridge_driver_t; --TODO determine where we want to declare the IP + signal dummy_ready : std_logic; + signal dummy_valid : std_logic; + signal dummy_data : std_logic_vector(31 downto 0); --signal gan_socbridge_WE_in : std_logic; --signal gan_socbridge_WE_out : std_logic; @@ -71,6 +76,29 @@ begin socbridge_driver_to_manager => socbridge_driver_to_manager ); + fifo_buffer_to_ip_inst : entity gan_buffer.fifo_buffer + port map( + clk => clk, + rst => rst, + ready_in => dummy_ready, + ready_out => ip_to_ganimede.socbridge.is_full_in, + valid_in => ganimede_to_ip.socbridge.write_enable_in, + valid_out => dummy_valid, + data_in => ganimede_to_ip.socbridge.payload, + data_out => dummy_data + ); + + fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer + port map( + clk => clk, + rst => rst, + ready_in => ganimede_to_ip.socbridge.is_full_out, + ready_out => dummy_ready, + valid_in => dummy_valid, + valid_out => ip_to_ganimede.socbridge.write_enable_out, + data_in => dummy_data, + data_out => ip_to_ganimede.socbridge.payload + ); --- LATER WE ADD OPTIMIZATIONS HERE --- diff --git a/src/gantry.toml b/src/gantry.toml index c650fd2..50209a7 100644 --- a/src/gantry.toml +++ b/src/gantry.toml @@ -38,139 +38,7 @@ path = "grlib-com-nx-2024.4-b4295/verification/socbridge" [libraries.techmap] vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/gencomp" - -[libraries.alltech] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/alltech" - -[libraries.altera_mf] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/altera_mf" - -[libraries.apa] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/apa" - -[libraries.artisan] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/artisan" - -[libraries.atc18] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/atc18" - -[libraries.axcelerator] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/axcelerator" - -[libraries.cust1] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/cust1" - -[libraries.cycloneiii] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/cycloneiii" - -[libraries.dware] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/dware" - -[libraries.ec] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/ec" - -[libraries.eclipsee] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/eclipsee" - -[libraries.fusion] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/fusion" - -[libraries.inferred] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/inferred" - -[libraries.grdware] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/grdware" - -[libraries.maps] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/maps" - -[libraries.nx] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/nx" - -[libraries.polarfire] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/polarfire" - -[libraries.nexus] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/nexus" - -[libraries.proasic3] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/proasic3" - -[libraries.proasic3e] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/proasic3e" - -[libraries.proasic3l] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/proasic3l" - -[libraries.saed32] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/saed32" - -[libraries.smartfusion2] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/smartfusion2" - -[libraries.stratixiii] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/stratixiii" - -[libraries.stratixii] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/stratixii" - -[libraries.stratixiv] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/stratixiv" - -[libraries.stratixv] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/stratixv" - -[libraries.umc18] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/umc18" - -[libraries.unisim] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/unisim" - -[libraries.virage90] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/virage90" - -[libraries.virage] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/virage" - -[libraries.virtex] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/virtex" - -[libraries.virtex5] -vhdl-version = "93c" -path = "grlib-com-nx-2024.4-b4295/lib/techmap/virtex5" +path = "grlib-com-nx-2024.4-b4295/lib/techmap" [libraries.opencores] vhdl-version = "93c" @@ -188,3 +56,6 @@ path = "grlib-com-nx-2024.4-b4295/lib/micron" vhdl-version = "93c" path = "grlib-com-nx-2024.4-b4295/verification/ahb2ahb" +[libraries.gan_buffer] +vhdl-version = "93c" +path = "fifo_buffer"