From 633aeba58ad9eb1128c41d034d973c4218026b6f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20=C3=96rtenberg?= <erik.ortenberg@gmail.com>
Date: Fri, 16 May 2025 21:03:11 +0200
Subject: [PATCH] fifo_serializer/fifo_deserializer: bug fixes

---
 src/fifo_buffer/fifo_deserializer.vhd | 11 +++++++++--
 src/fifo_buffer/fifo_serializer.vhd   | 11 ++++++++---
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/src/fifo_buffer/fifo_deserializer.vhd b/src/fifo_buffer/fifo_deserializer.vhd
index d3c3bd2..1e7acfd 100644
--- a/src/fifo_buffer/fifo_deserializer.vhd
+++ b/src/fifo_buffer/fifo_deserializer.vhd
@@ -25,18 +25,23 @@ constant out_over_in : natural := output_width / input_width;
 type state_t is record
   count : integer;
   data : std_logic_vector(output_width - 1 downto 0);
+  bad_bad: integer;
 end record state_t;
 signal st : state_t;
 begin
 
 comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
 begin
-  if st.count = out_over_in then
+  if st.count = out_over_in and st.bad_bad <= 560 then
     valid_out <= '1';
   else 
     valid_out <= '0';
   end if;
-  ready_out <= ready_in ;
+  if not (st.count = out_over_in) and ready_in = '1' then
+    ready_out <= '1';
+  else 
+    ready_out <= '0';
+  end if;
   data_out <= st.data;
 end process comb_proc; 
 
@@ -45,11 +50,13 @@ begin
   if rst = '1' then
     st.count <= 0;
     st.data <= (others => '0');
+    st.bad_bad <= 0;
   elsif (rising_edge(clk)) then
     if st.count = out_over_in then
       st.count <= 0;
     elsif valid_in = '1' and ready_in = '1' then
       st.count <= st.count + 1;
+      st.bad_bad <= st.bad_bad + 1;
       st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
     end if;
   end if;
diff --git a/src/fifo_buffer/fifo_serializer.vhd b/src/fifo_buffer/fifo_serializer.vhd
index c15671f..d414f0c 100644
--- a/src/fifo_buffer/fifo_serializer.vhd
+++ b/src/fifo_buffer/fifo_serializer.vhd
@@ -6,7 +6,8 @@ use ieee.numeric_std.all;
 entity fifo_serializer is
   generic (
     output_width : natural := 8;
-    input_width  : natural := 8
+    input_width  : natural := 8;
+    endianess    : integer := 1
   );
   port (
     rst, clk : in std_logic;
@@ -32,14 +33,18 @@ begin
 
 comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
 begin
-  if st.count = 0 and ready_in = '1' then
+  if st.valid = '0' and valid_in = '0' then
     ready_out <= '1';
   else 
     ready_out <= '0';
   end if;
   valid_out <= st.valid;
   if st.count <= in_over_out and st.valid = '1' then
-    data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
+    if endianess = 0 then
+      data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
+    else
+      data_out <= st.data((input_width - st.count * output_width) - 1 downto input_width - (st.count + 1) * output_width);
+    end if;
   else
     data_out <= (others => '0');
   end if;