testbench might work but ghdl broke so could not test
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@ -24,11 +24,18 @@ architecture tb of ganimede_tb is
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));
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signal ganimede_to_ext : ganimede_to_ext_t;
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signal ganimede_to_ip : ganimede_to_ip_t;
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signal ip_to_ganimede : ip_to_ganimede_t := (
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signal ganimede_to_cpu : controller_to_cpu_t;
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signal cpu_to_ganimede : cpu_to_controller_t := (
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driver_id => (others => '0'),
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address => (others => '0'),
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seq_mem_access_count => 0,
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cmd => (others => '0')
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);
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signal ip_to_ganimede : ip_to_ganimede_t := (socbridge => (
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payload => (others => '0'),
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write_enable_out => '0',
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is_full_in => '0'
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);
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));
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signal cpu_to_controller: cpu_to_controller_t := (
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driver_id => (others => '0'),
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address => (others => '0'),
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@ -78,10 +85,10 @@ architecture tb of ganimede_tb is
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begin
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ganimede_inst: entity ganimede.ganimede_toplevel
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port map(
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clk => clk,
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rst => rst,
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controller_to_socbridge_driver => controller_to_drivers.socbridge,
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socbridge_driver_to_controller => drivers_to_controller.socbridge,
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clk => clk,
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rst => rst,
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cpu_to_ganimede => cpu_to_ganimede,
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ganimede_to_cpu => ganimede_to_cpu,
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ext_to_ganimede => ext_to_ganimede,
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ganimede_to_ext => ganimede_to_ext,
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ip_to_ganimede => ip_to_ganimede,
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