testbench might work but ghdl broke so could not test

This commit is contained in:
Adam Magnusson 2025-03-17 12:16:20 +01:00
parent 88dcd19a47
commit 678afc4bd9

View File

@ -24,11 +24,18 @@ architecture tb of ganimede_tb is
));
signal ganimede_to_ext : ganimede_to_ext_t;
signal ganimede_to_ip : ganimede_to_ip_t;
signal ip_to_ganimede : ip_to_ganimede_t := (
signal ganimede_to_cpu : controller_to_cpu_t;
signal cpu_to_ganimede : cpu_to_controller_t := (
driver_id => (others => '0'),
address => (others => '0'),
seq_mem_access_count => 0,
cmd => (others => '0')
);
signal ip_to_ganimede : ip_to_ganimede_t := (socbridge => (
payload => (others => '0'),
write_enable_out => '0',
is_full_in => '0'
);
));
signal cpu_to_controller: cpu_to_controller_t := (
driver_id => (others => '0'),
address => (others => '0'),
@ -80,8 +87,8 @@ begin
port map(
clk => clk,
rst => rst,
controller_to_socbridge_driver => controller_to_drivers.socbridge,
socbridge_driver_to_controller => drivers_to_controller.socbridge,
cpu_to_ganimede => cpu_to_ganimede,
ganimede_to_cpu => ganimede_to_cpu,
ext_to_ganimede => ext_to_ganimede,
ganimede_to_ext => ganimede_to_ext,
ip_to_ganimede => ip_to_ganimede,