From 70275f624a3aa5eb822bbd42d8d817fe04d68f3a Mon Sep 17 00:00:00 2001 From: Adam Date: Mon, 7 Apr 2025 15:04:15 +0200 Subject: [PATCH] first version of management unit done --- src/management_unit/management_unit.vhd | 77 +++++++++++++++++++++ src/management_unit/management_unit_pkg.vhd | 42 +++++++++++ 2 files changed, 119 insertions(+) create mode 100644 src/management_unit/management_unit.vhd create mode 100644 src/management_unit/management_unit_pkg.vhd diff --git a/src/management_unit/management_unit.vhd b/src/management_unit/management_unit.vhd new file mode 100644 index 0000000..9f7febd --- /dev/null +++ b/src/management_unit/management_unit.vhd @@ -0,0 +1,77 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.MATH_REAL.all; +use ieee.numeric_std.all; +library manager; +use manager.management_types.all; +library ganimede; +use ganimede.io_types.all; + +entity management_unit is + port ( + clk, rst : in std_logic; + manager_to_controller : out manager_to_controller_t; + controller_to_manager : in controller_to_manager_t; + socbridge_driver_to_manager : in socbridge_driver_to_manager_t; + manager_to_socbridge_driver : out manager_to_socbridge_driver_t + ); + +end entity management_unit; + +architecture rtl of management_unit is + signal manager_state : manager_state_t; + signal write_address : manager_word_t; + signal read_address : manager_word_t; + signal msg_size : manager_word_t; +begin + +read_address <= manager_state.memory(to_integer(unsigned(read_address_index))); +write_address <= manager_state.memory(to_integer(unsigned(write_address_index))); + + +comb_proc: process(controller_to_manager, socbridge_driver_to_manager) +begin + -- Read data from manager to SoCBridge driver + manager_to_socbridge_driver.data <= manager_state.memory(to_integer(unsigned(socbridge_driver_to_manager.address))); + manager_to_socbridge_driver.valid <= '1'; +end process comb_proc; + +seq_proc: process(clk) +begin + if rising_edge(clk) then + if rst = '1' then + manager_state <= manager_state_reset_val; + else + -- Write data from SoCBridge driver to address + if socbridge_driver_to_manager.valid = '1' then + manager_state.memory(to_integer(unsigned(socbridge_driver_to_manager.address))) <= socbridge_driver_to_manager.data; + if socbridge_driver_to_manager.address = read_address_index + or socbridge_driver_to_manager.address = write_address_index then + -- CLEAR BUFFER TO IP CORE + end if; + end if; + + -- Is there a read instruction in memory + if read_address /= (others => '0') and controller_to_manager.ready = '1' then + manager_to_controller.address <= read_address; + manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present + manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size)); + manager_to_controller.cmd <= "10"; + -- Is there a write instruction in memory + elsif write_address /= (others => '0') and controller_to_manager.ready = '1' then + manager_to_controller.address <= write_address; + manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present + manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size)); + manager_to_controller.cmd <= "01"; + else + -- No instruction present in memory, all zeroes to control unit + manager_to_controller.address <= (others => '0'); + manager_to_controller.driver_id <= "0"; -- Only supprts one driver at present + manager_to_controller.seq_mem_access_count <= 0; + manager_to_controller.cmd <= "00"; + end if; + end if; + end if; +end process seq_proc; + +end architecture rtl ; diff --git a/src/management_unit/management_unit_pkg.vhd b/src/management_unit/management_unit_pkg.vhd new file mode 100644 index 0000000..3be5eac --- /dev/null +++ b/src/management_unit/management_unit_pkg.vhd @@ -0,0 +1,42 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.MATH_REAL.all; +library ganimede; +use ganimede.io_types.all; + +package management_types is + constant WORD_SIZE : natural := 32; + subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0); + constant mem_words : natural := 64; + type memory_t is array (0 to mem_words - 1) of manager_word_t; + + -- Index in memory array where memory read address is kept. + -- Read is active while it is not all zero. + constant read_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0'); + -- Index in memory array where memory write address is kept. + -- Write is active while it is not all zero. Mutex with read address + constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0') & '1'; + constant access_size : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0') & "10"; + + -- Status register for debugging + type manager_state_t is record + memory : memory_t; + data_out : manager_word_t; + end record manager_state_t; + + -- reset value of status register + constant manager_state_reset_val : manager_state_t := ((others => (others => '0')), x"0000"); + + type socbridge_driver_to_manager_t is record + address : manager_word_t; + data : manager_word_t; + valid: std_logic; + end record socbridge_driver_to_manager_t; + + type manager_to_socbridge_driver_t is record + data : manager_word_t; + valid : std_logic; + ready : std_logic; + end record manager_to_socbridge_driver_t; + +end package;