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Control unit tested and seems to work for the requirements of the basic version

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Adam Magnusson 2025-03-04 14:54:15 +01:00 committed by Erik Örtenberg
parent 4c4d62554f
commit 7a24dc8feb
3 changed files with 18 additions and 7 deletions
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7
src/control_unit.vhd
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@ -19,7 +19,7 @@ architecture behave of control_unit is
address: std_logic_vector(address_width - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
ready: std_logic; ready, is_write: std_logic;
end record state_t; end record state_t;
signal state: state_t; signal state: state_t;
@ -38,6 +38,7 @@ begin
control_out.address <= state.address; control_out.address <= state.address;
control_out.seq_mem_access_count <= state.seq_mem_access_count; control_out.seq_mem_access_count <= state.seq_mem_access_count;
control_out.ready <= state.ready; control_out.ready <= state.ready;
control_out.is_write <= state.is_write;
end process comb_proc; end process comb_proc;
sync_proc: process(clk, state) sync_proc: process(clk, state)
@ -47,13 +48,15 @@ begin
state <= ((others => '0'), state <= ((others => '0'),
(others => '0'), (others => '0'),
(others => '0'), (others => '0'),
'1'); '1',
'0');
else else
state.ready <= not ored; state.ready <= not ored;
if ored = '0' then if ored = '0' then
state.address <= control_in.address; state.address <= control_in.address;
state.seq_mem_access_count <= control_in.seq_mem_access_count; state.seq_mem_access_count <= control_in.seq_mem_access_count;
state.curr_driver <= control_in.driver_id; state.curr_driver <= control_in.driver_id;
state.is_write <= control_in.is_write;
end if; end if;
end if; end if;
end if; end if;

15
src/control_unit_tb.vhd
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@ -17,12 +17,14 @@ architecture tb of control_unit_tb is
(others => '0'), (others => '0'),
(others => '0'), (others => '0'),
(others => '0'), (others => '0'),
"00000011"); (others => '0'),
'0');
signal control_output: control_unit_out_t := ( signal control_output: control_unit_out_t := (
(others => '0'), (others => '0'),
(others => '0'), (others => '0'),
(others => '1'), (others => '1'),
'1'); '1',
'0');
signal current_driver : std_logic_vector(2 downto 0) := "000"; signal current_driver : std_logic_vector(2 downto 0) := "000";
shared variable word_counter: natural := 0; shared variable word_counter: natural := 0;
@ -52,7 +54,8 @@ begin
control_input.driver_id <= "010"; control_input.driver_id <= "010";
control_input.active_driver <= "000"; control_input.active_driver <= "000";
control_input.address <= x"F0F0F0F0"; control_input.address <= x"F0F0F0F0";
control_input.seq_mem_access_count <= "00000111"; control_input.seq_mem_access_count <= "00000011";
control_input.is_write <= '1';
word_counter := 3; word_counter := 3;
wait for cycle; wait for cycle;
current_driver <= "010"; current_driver <= "010";
@ -60,7 +63,7 @@ begin
report "entering loop with word_counter" & integer'image(word_counter); report "entering loop with word_counter" & integer'image(word_counter);
for_loop: for i in word_counter - 1 downto 0 loop for_loop: for i in word_counter - 1 downto 0 loop
wait for cycle; wait for cycle;
report "word counter is " & integer'image(word_counter); report "words remaining are " & integer'image(i);
end loop for_loop; end loop for_loop;
control_input.active_driver <= "000"; control_input.active_driver <= "000";
@ -76,7 +79,11 @@ begin
wait for cycle; wait for cycle;
assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error; assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error; assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
assert control_output.is_write = '0' report "Incorrect memory op from control_unit" severity error;
wait for 5 * cycle; wait for 5 * cycle;
reset <= '1';
report "Monitor process done"; report "Monitor process done";
wait; wait;
end process monitor_proc; end process monitor_proc;

3
src/io_type_pkg.vhd
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@ -23,13 +23,14 @@ package io_types is
driver_id: std_logic_vector(number_of_drivers - 1 downto 0); driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
address: std_logic_vector(address_width - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
ready: std_logic; ready, is_write: std_logic;
end record control_unit_out_t; end record control_unit_out_t;
type control_unit_in_t is record type control_unit_in_t is record
driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0); driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
address: std_logic_vector(address_width - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
is_write: std_logic;
end record control_unit_in_t; end record control_unit_in_t;
--- PROTOCOL INFORMATION --- --- PROTOCOL INFORMATION ---
constant interface_inst : interface_inst_t := ( constant interface_inst : interface_inst_t := (