From 88dcd19a477740fc460316405e3a203a016e6294 Mon Sep 17 00:00:00 2001 From: Adam Date: Fri, 14 Mar 2025 17:01:15 +0100 Subject: [PATCH] Refactored controller types to support multiple drivers. Also started ganimede tb --- .../control_socbridge_tb.vhd | 42 ++-- src/controller/control_unit.vhd | 22 +- src/controller/control_unit_tb.vhd | 18 +- src/ganimede/ganimede.vhd | 84 +++---- src/ganimede/ganimede_tb.vhd | 208 ++++++++++++++++++ src/ganimede/io_type_pkg.vhd | 96 ++++---- src/gantry.toml | 21 ++ src/socbridge/socbridge_driver.vhd | 30 +-- src/socbridge/socbridge_driver_tb.vhd | 42 ++-- src/socbridge/socbridge_driver_tb_pkg.vhd | 2 +- src/vhdl_ls.toml | 3 +- 11 files changed, 400 insertions(+), 168 deletions(-) create mode 100644 src/ganimede/ganimede_tb.vhd create mode 100644 src/gantry.toml diff --git a/src/control_socbridge_merge/control_socbridge_tb.vhd b/src/control_socbridge_merge/control_socbridge_tb.vhd index dc15769..28e68c4 100644 --- a/src/control_socbridge_merge/control_socbridge_tb.vhd +++ b/src/control_socbridge_merge/control_socbridge_tb.vhd @@ -23,8 +23,8 @@ architecture tb of control_socbridge_tb is control => (others => '0') ); signal socbridge_driver_to_ext : socbridge_driver_to_ext_t; - signal socbridge_driver_to_buffer : socbridge_driver_to_buffer_t; - signal buffer_to_socbridge_driver : buffer_to_socbridge_driver_t := ( + signal socbridge_driver_to_ip : socbridge_driver_to_ip_t; + signal ip_to_socbridge_driver : ip_to_socbridge_driver_t := ( payload => (others => '0'), write_enable_out => '0', is_full_in => '0' @@ -35,9 +35,9 @@ architecture tb of control_socbridge_tb is seq_mem_access_count => 0, cmd => "00" ); - signal socbridge_driver_to_controller: socbridge_driver_to_controller_t := (is_active => '0'); + signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0')); signal controller_to_cpu: controller_to_cpu_t; - signal controller_to_socbridge_driver: controller_to_socbridge_driver_t; + signal controller_to_drivers: controller_to_drivers_t; signal curr_word : std_logic_vector(ext_to_socbridge_driver.payload'length - 1 downto 0); signal expected_out : std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0); @@ -80,12 +80,12 @@ begin port map( clk => clk, rst => rst, - controller_to_socbridge_driver => controller_to_socbridge_driver, - socbridge_driver_to_controller => socbridge_driver_to_controller, + controller_to_socbridge_driver => controller_to_drivers.socbridge, + socbridge_driver_to_controller => drivers_to_controller.socbridge, ext_to_socbridge_driver => ext_to_socbridge_driver, socbridge_driver_to_ext => socbridge_driver_to_ext, - buffer_to_socbridge_driver => buffer_to_socbridge_driver, - socbridge_driver_to_buffer => socbridge_driver_to_buffer + ip_to_socbridge_driver => ip_to_socbridge_driver, + socbridge_driver_to_ip => socbridge_driver_to_ip ); controller_unit_inst: entity controller.control_unit @@ -94,8 +94,8 @@ begin rst => rst, cpu_to_controller => cpu_to_controller, controller_to_cpu => controller_to_cpu, - socbridge_driver_to_controller => socbridge_driver_to_controller, - controller_to_socbridge_driver => controller_to_socbridge_driver + drivers_to_controller => drivers_to_controller, + controller_to_drivers => controller_to_drivers ); ext_to_socbridge_driver.control(1) <= clk; @@ -121,21 +121,21 @@ begin rst <= '0'; cpu_to_controller.address <= x"FA0FA0FA"; cpu_to_controller.cmd <= "01"; - wait until socbridge_driver_to_controller.is_active = '1'; + wait until drivers_to_controller.socbridge.is_active = '1'; report "Task received in driver, awaiting completion..."; cpu_to_controller.address <= (others => '0'); cpu_to_controller.cmd <= "00"; - wait until socbridge_driver_to_controller.is_active = '0'; + wait until drivers_to_controller.socbridge.is_active = '0'; wait for CLK_PERIOD; report "Task completed in driver, sending next task..."; cpu_to_controller.address <= x"FA0FA0FA"; cpu_to_controller.cmd <= "10"; wait for CLK_PERIOD; - wait until socbridge_driver_to_controller.is_active = '1'; + wait until drivers_to_controller.socbridge.is_active = '1'; report "Task received in driver, awaiting completion..."; cpu_to_controller.address <= (others => '0'); cpu_to_controller.cmd <= "00"; - wait until socbridge_driver_to_controller.is_active = '0'; + wait until drivers_to_controller.socbridge.is_active = '0'; wait for CLK_PERIOD; report "Task completed in driver, ending simulation stimulus"; cpu_to_controller.address <= (others => '0'); @@ -197,19 +197,19 @@ begin internal_stimulus: process variable input : positive := 1; begin - buffer_to_socbridge_driver.is_full_in <= '0'; - buffer_to_socbridge_driver.write_enable_out <= '0'; + ip_to_socbridge_driver.is_full_in <= '0'; + ip_to_socbridge_driver.write_enable_out <= '0'; wait for 3 * CLK_PERIOD; -- stimulus goes here - buffer_to_socbridge_driver.write_enable_out <= '1'; - buffer_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, buffer_to_socbridge_driver.payload'length)); + ip_to_socbridge_driver.write_enable_out <= '1'; + ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, ip_to_socbridge_driver.payload'length)); input := input + 1 mod 256; - wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0'; + wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0'; wait until falling_edge(clk); for x in 0 to 1000 loop - buffer_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, buffer_to_socbridge_driver.payload'length)); + ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, ip_to_socbridge_driver.payload'length)); input := input + 1 mod 256; - wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0'; + wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0'; wait until falling_edge(clk); end loop; wait; diff --git a/src/controller/control_unit.vhd b/src/controller/control_unit.vhd index 66f4870..d8d6975 100644 --- a/src/controller/control_unit.vhd +++ b/src/controller/control_unit.vhd @@ -7,11 +7,11 @@ use ganimede.io_types.all; entity control_unit is port ( - clk, rst : in std_logic; - cpu_to_controller : in cpu_to_controller_t; - controller_to_cpu : out controller_to_cpu_t; - socbridge_driver_to_controller : in socbridge_driver_to_controller_t; - controller_to_socbridge_driver : out controller_to_socbridge_driver_t + clk, rst : in std_logic; + cpu_to_controller : in cpu_to_controller_t; + controller_to_cpu : out controller_to_cpu_t; + drivers_to_controller : in drivers_to_controller_t; + controller_to_drivers : out controller_to_drivers_t ); end entity control_unit; @@ -31,17 +31,17 @@ architecture behave of control_unit is begin - comb_proc: process(cpu_to_controller, socbridge_driver_to_controller, state) + comb_proc: process(cpu_to_controller, drivers_to_controller, state) begin ored := '0'; ready_reduction: for i in 0 to number_of_drivers - 1 loop - ored := ored or socbridge_driver_to_controller.is_active; + ored := ored or drivers_to_controller.socbridge.is_active; end loop ready_reduction; - controller_to_socbridge_driver.request <= state.curr_driver; - controller_to_socbridge_driver.address <= state.address; - controller_to_socbridge_driver.seq_mem_access_count <= state.seq_mem_access_count; + controller_to_drivers.socbridge.request <= state.curr_driver; + controller_to_drivers.socbridge.address <= state.address; + controller_to_drivers.socbridge.seq_mem_access_count <= state.seq_mem_access_count; controller_to_cpu.ready <= state.ready; - controller_to_socbridge_driver.instruction <= state.instruction; + controller_to_drivers.socbridge.instruction <= state.instruction; end process comb_proc; sync_proc: process(clk, state) diff --git a/src/controller/control_unit_tb.vhd b/src/controller/control_unit_tb.vhd index 905166d..71ecc4b 100644 --- a/src/controller/control_unit_tb.vhd +++ b/src/controller/control_unit_tb.vhd @@ -19,9 +19,9 @@ architecture tb of control_unit_tb is (others => '0'), 0, "00"); - signal socbridge_driver_to_controller: socbridge_driver_to_controller_t := (is_active => '0'); + signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0')); signal controller_to_cpu: controller_to_cpu_t; - signal controller_to_socbridge_driver: controller_to_socbridge_driver_t; + signal controller_to_drivers: controller_to_drivers_t; signal current_driver : std_logic_vector(0 downto 0) := "0"; shared variable word_counter: natural := 0; @@ -42,8 +42,8 @@ begin rst => reset, cpu_to_controller => cpu_to_controller, controller_to_cpu => controller_to_cpu, - socbridge_driver_to_controller => socbridge_driver_to_controller, - controller_to_socbridge_driver => controller_to_socbridge_driver + drivers_to_controller => drivers_to_controller, + controller_to_drivers => controller_to_drivers ); stimulus_proc: process @@ -51,7 +51,7 @@ begin wait for cycle; cpu_to_controller.driver_id <= "1"; - socbridge_driver_to_controller.is_active <= '0'; + drivers_to_controller.socbridge.is_active <= '0'; cpu_to_controller.address <= x"F0F0F0F0"; cpu_to_controller.seq_mem_access_count <= 3; cpu_to_controller.cmd <= "01"; @@ -65,7 +65,7 @@ begin report "words remaining are " & integer'image(i); end loop for_loop; - socbridge_driver_to_controller.is_active <= '0'; + drivers_to_controller.socbridge.is_active <= '0'; report "Stim process done"; wait; end process stimulus_proc; @@ -76,9 +76,9 @@ begin wait for cycle; wait for cycle; - assert controller_to_socbridge_driver.request = '1' report "Incorrect driver_id from control_unit" severity error; - assert controller_to_socbridge_driver.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error; - assert controller_to_socbridge_driver.instruction = WRITE report "Incorrect memory op from control_unit" severity error; + assert controller_to_drivers.socbridge.request = '1' report "Incorrect driver_id from control_unit" severity error; + assert controller_to_drivers.socbridge.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error; + assert controller_to_drivers.socbridge.instruction = WRITE report "Incorrect memory op from control_unit" severity error; wait for 5 * cycle; reset <= '1'; diff --git a/src/ganimede/ganimede.vhd b/src/ganimede/ganimede.vhd index cac2fc7..4c29064 100644 --- a/src/ganimede/ganimede.vhd +++ b/src/ganimede/ganimede.vhd @@ -1,26 +1,32 @@ library IEEE; use IEEE.std_logic_1164.all; -library work; -use work.io_types; +library ganimede; +use ganimede.io_types.all; library socbridge; use socbridge.socbridge_driver_tb_pkg.all; library controller; -entity ganimede is +entity ganimede_toplevel is port ( - clk : in std_logic; - reset : in std_logic; - ext_interface_in : in ext_interface_in_t; - ext_interface_out : out ext_interface_out_t; - int_interface_in : in int_interface_in_t; - int_interface_out : out int_interface_out_t + clk : in std_logic; + rst : in std_logic; + cpu_to_ganimede : in cpu_to_controller_t; + ganimede_to_cpu : out controller_to_cpu_t; + ext_to_ganimede : in ext_to_ganimede_t; + ganimede_to_ext : out ganimede_to_ext_t; + ip_to_ganimede : in ip_to_ganimede_t; + ganimede_to_ip : out ganimede_to_ip_t ); -end entity ganimede; -architecture rtl of ganimede is +end entity ganimede_toplevel; +architecture rtl of ganimede_toplevel is --- SIGNAL DECLERATIONS --- - signal gan_int_interface_out : int_interface_out_t; - signal gan_ext_interface_in : ext_interface_in_t; - signal gan_ext_interface_out : ext_interface_out_t; + signal ext_to_drivers : ext_to_ganimede_t; + signal drivers_to_ext : ganimede_to_ext_t; + signal drivers_to_ip : ganimede_to_ip_t; + signal ip_to_drivers : ip_to_ganimede_t; + signal drivers_to_controller : drivers_to_controller_t; + signal controller_to_drivers : controller_to_drivers_t; + --signal gan_socbridge_WE_in : std_logic; --signal gan_socbridge_WE_out : std_logic; @@ -40,34 +46,34 @@ architecture rtl of ganimede is -- data_out : out std_logic_vector(WIDTH - 1 downto 0) -- ); --end component; - - component socbridge_driver is - port( - clk : in std_logic; - reset : in std_logic; - ext_in : in ext_to_socbridge_driver_t; - ext_out : out socbridge_driver_to_ext_t; - int_in : out buffer_to_socbridge_driver_t; - int_out : in socbridge_driver_to_buffer_t - ); - end component; - begin --- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS --- - gan_int_interface_in <= int_interface_in; - int_interface_out <= gan_int_interface_out; - gan_ext_interface_in <= ext_interface_in; - ext_interface_out <= gan_ext_interface_out; - + ip_to_drivers <= ip_to_ganimede; + ganimede_to_ip <= drivers_to_ip; + ext_to_drivers <= ext_to_ganimede; + ganimede_to_ext <= drivers_to_ext; + --- DRIVER INSTANTIATION --- - socbridge_driver_inst: entity socbridge.socbridge_driver - port map( - clk => clk, - reset => reset, - ext_in => gan_ext_interface_in.socbridge, - ext_out => gan_ext_interface_out.socbridge, - int_in => gan_int_interface_in.socbridge, - int_out => gan_int_interface_out.socbridge + socbridge_inst: entity socbridge.socbridge_driver + port map( + clk => clk, + rst => rst, + controller_to_socbridge_driver => controller_to_drivers.socbridge, + socbridge_driver_to_controller => drivers_to_controller.socbridge, + ext_to_socbridge_driver => ext_to_ganimede.socbridge, + socbridge_driver_to_ext => ganimede_to_ext.socbridge, + ip_to_socbridge_driver => ip_to_ganimede.socbridge, + socbridge_driver_to_ip => ganimede_to_ip.socbridge + ); + + controller_unit_inst: entity controller.control_unit + port map( + clk => clk, + rst => rst, + cpu_to_controller => cpu_to_ganimede, + controller_to_cpu => ganimede_to_cpu, + drivers_to_controller => drivers_to_controller, + controller_to_drivers => controller_to_drivers ); --- LATER WE ADD OPTIMIZATIONS HERE --- diff --git a/src/ganimede/ganimede_tb.vhd b/src/ganimede/ganimede_tb.vhd new file mode 100644 index 0000000..a8c6f6c --- /dev/null +++ b/src/ganimede/ganimede_tb.vhd @@ -0,0 +1,208 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; +library ganimede; +use ganimede.io_types.all; +library socbridge; +use socbridge.socbridge_driver_tb_pkg.all; +library controller; + +entity ganimede_tb is +end entity ganimede_tb; + +architecture tb of ganimede_tb is + + constant CLK_PERIOD : Time := 10 ns; + constant SIMULATION_CYCLE_COUNT : integer := 2000; + signal clk, rst : std_logic := '0'; + signal controller_to_socbridge_driver_cmd : command_t; + signal controller_to_socbridge_driver_address : std_logic_vector(31 downto 0); + signal cmd_size : positive; + signal ext_to_ganimede : ext_to_ganimede_t := (socbridge => ( + payload => (others => '0'), + control => (others => '0') + )); + signal ganimede_to_ext : ganimede_to_ext_t; + signal ganimede_to_ip : ganimede_to_ip_t; + signal ip_to_ganimede : ip_to_ganimede_t := ( + payload => (others => '0'), + write_enable_out => '0', + is_full_in => '0' + ); + signal cpu_to_controller: cpu_to_controller_t := ( + driver_id => (others => '0'), + address => (others => '0'), + seq_mem_access_count => 0, + cmd => "00" + ); + signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0')); + signal controller_to_cpu: controller_to_cpu_t; + signal controller_to_drivers: controller_to_drivers_t; + + signal curr_word : std_logic_vector(ext_to_ganimede.socbridge.payload'length - 1 downto 0); + signal expected_out : std_logic_vector(ganimede_to_ext.socbridge.payload'length - 1 downto 0); + + procedure fail(error_msg : string) is + begin + wait for CLK_PERIOD; + report "Simulation ending due to: " & error_msg & ". Shutting down..." severity FAILURE; + end procedure; + + procedure check_next_state(correct_state: state_t) is + begin + if(not (correct_state = G_next_state)) then + report "Next State is not what was expected, found " & state_t'image(G_next_state) + & " but expected " & state_t'image(correct_state) severity error; + fail("Next State"); + end if; + end procedure; + + procedure check_data_out(correct_data: std_logic_vector(ganimede_to_ext.socbridge.payload'length - 1 downto 0)) is + begin + if(not (correct_data = ganimede_to_ext.socbridge.payload)) then + report "Data out is not what was expected, found " & to_string(ganimede_to_ext.socbridge.payload) + & " but expected " & to_string(correct_data) severity error; + fail("Data out"); + end if; + end procedure; + + procedure check_parity(correct_data: std_logic_vector(ganimede_to_ext.socbridge.payload'length - 1 downto 0)) is + begin + if(not (calc_parity(correct_data) = calc_parity(ganimede_to_ext.socbridge.payload))) then + report "Parity out is not what was expected, found " & std_logic'image(calc_parity(ganimede_to_ext.socbridge.payload)) + & " but expected " & std_logic'image(calc_parity(correct_data)) severity error; + fail("Parity out"); + end if; + end procedure; + +begin + ganimede_inst: entity ganimede.ganimede_toplevel + port map( + clk => clk, + rst => rst, + controller_to_socbridge_driver => controller_to_drivers.socbridge, + socbridge_driver_to_controller => drivers_to_controller.socbridge, + ext_to_ganimede => ext_to_ganimede, + ganimede_to_ext => ganimede_to_ext, + ip_to_ganimede => ip_to_ganimede, + ganimede_to_ip => ganimede_to_ip + ); + + ext_to_ganimede.socbridge.control(1) <= clk; + controller_clock_proc: process + begin + for i in 0 to SIMULATION_CYCLE_COUNT - 1 loop + wait for CLK_PERIOD / 2; + clk <= not clk; + end loop; + wait; + end process controller_clock_proc; + + stimulus_proc: process + begin + report "Starting Simulation Stimulus!"; + rst <= '1'; + cpu_to_controller.address <= (others => '0'); + cpu_to_controller.cmd <= "00"; + cpu_to_controller.driver_id <= "1"; + cpu_to_controller.seq_mem_access_count <= 256; + wait for 3 * CLK_PERIOD; + report "Reset grace period ended, starting stimulus..."; + rst <= '0'; + cpu_to_controller.address <= x"FA0FA0FA"; + cpu_to_controller.cmd <= "01"; + wait until drivers_to_controller.socbridge.is_active = '1'; + report "Task received in driver, awaiting completion..."; + cpu_to_controller.address <= (others => '0'); + cpu_to_controller.cmd <= "00"; + wait until drivers_to_controller.socbridge.is_active = '0'; + wait for CLK_PERIOD; + report "Task completed in driver, sending next task..."; + cpu_to_controller.address <= x"FA0FA0FA"; + cpu_to_controller.cmd <= "10"; + wait for CLK_PERIOD; + wait until drivers_to_controller.socbridge.is_active = '1'; + report "Task received in driver, awaiting completion..."; + cpu_to_controller.address <= (others => '0'); + cpu_to_controller.cmd <= "00"; + wait until drivers_to_controller.socbridge.is_active = '0'; + wait for CLK_PERIOD; + report "Task completed in driver, ending simulation stimulus"; + cpu_to_controller.address <= (others => '0'); + cpu_to_controller.cmd <= "00"; + cpu_to_controller.driver_id <= "0"; + cpu_to_controller.seq_mem_access_count <= 0; + + wait; + end process stimulus_proc; + + external_stimulus_signal: process(curr_word) + begin + ext_to_ganimede.socbridge.payload <= curr_word; + ext_to_ganimede.socbridge.control(0) <= calc_parity(curr_word); + end process external_stimulus_signal; + + external_stimulus: process + variable input : positive := 1; + begin + wait for CLK_PERIOD / 1000; + curr_word <= "00000000"; + wait for 999 * CLK_PERIOD / 1000; + wait for 2 * CLK_PERIOD; + wait for CLK_PERIOD / 2; + wait for 10* CLK_PERIOD; + curr_word <= "00001001"; + wait for CLK_PERIOD; + curr_word <= "00000000"; + wait for CLK_PERIOD * 140; + curr_word <= "00101001"; + wait for CLK_PERIOD; + curr_word <= "00000000"; + wait for CLK_PERIOD * 140; + curr_word <= "00101001"; + wait for CLK_PERIOD; + curr_word <= "00000000"; + wait for CLK_PERIOD * 20; + curr_word <= "01100111"; + wait for CLK_PERIOD; + for x in 0 to 127 loop + curr_word <= std_logic_vector(to_unsigned(input, 8)); + input := input + 1 mod 256; + wait for CLK_PERIOD; + end loop; + curr_word <= "00000000"; + wait for CLK_PERIOD * 140; + wait for CLK_PERIOD * 20; + curr_word <= "01100111"; + wait for CLK_PERIOD; + for x in 0 to 127 loop + curr_word <= std_logic_vector(to_unsigned(input, 8)); + input := input + 1 mod 256; + wait for CLK_PERIOD; + end loop; + + wait; + end process external_stimulus; + + internal_stimulus: process + variable input : positive := 1; + begin + ip_to_ganimede.socbridge.is_full_in <= '0'; + ip_to_ganimede.socbridge.write_enable_out <= '0'; + wait for 3 * CLK_PERIOD; + -- stimulus goes here + ip_to_ganimede.socbridge.write_enable_out <= '1'; + ip_to_ganimede.socbridge.payload <= std_logic_vector(to_unsigned(input, ip_to_ganimede.socbridge.payload'length)); + input := input + 1 mod 256; + wait until rising_edge(clk) and ganimede_to_ip.socbridge.is_full_out = '0'; + wait until falling_edge(clk); + for x in 0 to 1000 loop + ip_to_ganimede.socbridge.payload <= std_logic_vector(to_unsigned(input, ip_to_ganimede.socbridge.payload'length)); + input := input + 1 mod 256; + wait until rising_edge(clk) and ganimede_to_ip.socbridge.is_full_out = '0'; + wait until falling_edge(clk); + end loop; + wait; + end process internal_stimulus; + +end architecture tb; diff --git a/src/ganimede/io_type_pkg.vhd b/src/ganimede/io_type_pkg.vhd index ed67ad3..62ab39d 100644 --- a/src/ganimede/io_type_pkg.vhd +++ b/src/ganimede/io_type_pkg.vhd @@ -5,64 +5,52 @@ use IEEE.MATH_REAL.all; package io_types is --- CONSTANTS --- - constant number_of_drivers: natural := 1; - constant address_width: natural := 32; - constant seq_vector_length: natural := 8; - constant inst_word_width: natural := 2; + constant number_of_drivers : natural := 1; + constant address_width : natural := 32; + constant inst_word_width : natural := 2; --- STANDARD TYPES --- type instruction_command_t is (NO_OP, READ, WRITE); type ext_protocol_def_t is record name: string (1 to 20); - payload_width: natural; - control_width_in, control_width_out: natural; + payload_width : natural; + control_width_in, control_width_out : natural; end record ext_protocol_def_t; type interface_inst_t is record - socbridge: ext_protocol_def_t; + socbridge : ext_protocol_def_t; end record interface_inst_t; --- CONTROL UNIT --- type cpu_to_controller_t is record - driver_id: std_logic_vector(number_of_drivers - 1 downto 0); - address: std_logic_vector(address_width - 1 downto 0); - seq_mem_access_count: integer; - cmd: std_logic_vector(1 downto 0); + driver_id : std_logic_vector(number_of_drivers - 1 downto 0); + address : std_logic_vector(address_width - 1 downto 0); + seq_mem_access_count : integer; + cmd : std_logic_vector(1 downto 0); end record cpu_to_controller_t; type controller_to_cpu_t is record - ready: std_logic; + ready : std_logic; end record controller_to_cpu_t; - --type controller_to_socbridge_driver_t is record - -- driver_id: std_logic_vector(number_of_drivers - 1 downto 0); - -- address: std_logic_vector(address_width - 1 downto 0); - -- seq_mem_access_count: integer; - -- instruction: instruction_command_t; - --end record controller_to_socbridge_driver_t; - - --type socbridge_driver_to_controller_t is record - -- active_driver: std_logic_vector(number_of_drivers - 1 downto 0); - --end record socbridge_driver_to_controller_t; - - type socbridge_driver_to_controller_t is record - is_active : std_logic; - end record socbridge_driver_to_controller_t; - - type controller_to_socbridge_driver_t is record - request: std_logic; - address: std_logic_vector(address_width - 1 downto 0); - seq_mem_access_count: integer; - instruction: instruction_command_t; - end record controller_to_socbridge_driver_t; - --- PROTOCOL INFORMATION --- constant interface_inst : interface_inst_t := ( socbridge => ("SoCBridge ", 8, 2, 2) - ); + ); --- AUTOGENERATED TYPES --- + type socbridge_driver_to_controller_t is record + is_active : std_logic; + end record socbridge_driver_to_controller_t; + + type controller_to_socbridge_driver_t is record + request : std_logic; + address : std_logic_vector(address_width - 1 downto 0); + seq_mem_access_count : integer; + instruction : instruction_command_t; + end record controller_to_socbridge_driver_t; + type ext_to_socbridge_driver_t is record payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0); control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0); @@ -73,30 +61,38 @@ package io_types is control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0); end record socbridge_driver_to_ext_t; - type socbridge_driver_to_buffer_t is record + type socbridge_driver_to_ip_t is record payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0); write_enable_in, is_full_out : std_logic; - end record socbridge_driver_to_buffer_t; + end record socbridge_driver_to_ip_t; - type buffer_to_socbridge_driver_t is record + type ip_to_socbridge_driver_t is record payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0); write_enable_out, is_full_in : std_logic; - end record buffer_to_socbridge_driver_t; + end record ip_to_socbridge_driver_t; - type ext_interface_in_t is record - socbridge : ext_to_socbridge_driver_t; - end record ext_interface_in_t; + type controller_to_drivers_t is record + socbridge : controller_to_socbridge_driver_t; + end record controller_to_drivers_t; - type ext_interface_out_t is record + type drivers_to_controller_t is record + socbridge : socbridge_driver_to_controller_t; + end record drivers_to_controller_t; + + type ext_to_ganimede_t is record + socbridge : ext_to_socbridge_driver_t; + end record ext_to_ganimede_t; + + type ganimede_to_ext_t is record socbridge : socbridge_driver_to_ext_t; - end record ext_interface_out_t; + end record ganimede_to_ext_t; - type int_interface_out_t is record - socbridge : socbridge_driver_to_buffer_t; - end record int_interface_out_t; + type ganimede_to_ip_t is record + socbridge : socbridge_driver_to_ip_t; + end record ganimede_to_ip_t; - type int_interface_in_t is record - socbridge : buffer_to_socbridge_driver_t; - end record int_interface_in_t; + type ip_to_ganimede_t is record + socbridge : ip_to_socbridge_driver_t; + end record ip_to_ganimede_t; end package io_types; diff --git a/src/gantry.toml b/src/gantry.toml new file mode 100644 index 0000000..cae03f7 --- /dev/null +++ b/src/gantry.toml @@ -0,0 +1,21 @@ +title = "ganimede" +createdAt = "2025-03-14" +maintainer = "" +email = "" +version = "0.0.1" + +[libraries.socbridge] +vhdl-version = "93" +path = "socbridge" + +[libraries.ganimede] +vhdl-version = "93" +path = "ganimede" + +[libraries.controller] +vhdl-version = "93" +path = "controller" + +[libraries.control_socbridge_merge] +vhdl-version = "93" +path = "control_socbridge_merge" diff --git a/src/socbridge/socbridge_driver.vhd b/src/socbridge/socbridge_driver.vhd index 449a32e..009fd33 100644 --- a/src/socbridge/socbridge_driver.vhd +++ b/src/socbridge/socbridge_driver.vhd @@ -15,8 +15,8 @@ entity socbridge_driver is socbridge_driver_to_controller : out socbridge_driver_to_controller_t; ext_to_socbridge_driver : in ext_to_socbridge_driver_t; socbridge_driver_to_ext : out socbridge_driver_to_ext_t; - socbridge_driver_to_buffer : out socbridge_driver_to_buffer_t; - buffer_to_socbridge_driver : in buffer_to_socbridge_driver_t + ip_to_socbridge_driver : in ip_to_socbridge_driver_t; + socbridge_driver_to_ip : out socbridge_driver_to_ip_t ); end entity socbridge_driver; @@ -77,7 +77,7 @@ begin READ_RESPONSE when "01000", READ_RESPONSE when "01100", NO_OP when others; - comb_proc: process(ext_to_socbridge_driver, buffer_to_socbridge_driver, curr_response, st, controller_to_socbridge_driver, trans_st) + comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver, curr_response, st, controller_to_socbridge_driver, trans_st) begin -- Outputs socbridge_driver_to_ext <= create_io_type_out_from_ext_protocol(st.socbridge_driver_to_ext_reg); @@ -194,9 +194,9 @@ begin --- Combinatorial output based on current state --- socbridge_driver_to_ext_data_cmd := (others => '0'); - socbridge_driver_to_buffer.is_full_out <= '1'; - socbridge_driver_to_buffer.write_enable_in <= '0'; - socbridge_driver_to_buffer.payload <= (others => '0'); + socbridge_driver_to_ip.is_full_out <= '1'; + socbridge_driver_to_ip.write_enable_in <= '0'; + socbridge_driver_to_ip.payload <= (others => '0'); case st.curr_state is when IDLE => if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then @@ -209,13 +209,13 @@ begin if st.curr_cmd = WRITE_ADD then socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0); else - socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload; - socbridge_driver_to_buffer.is_full_out <= '0'; + socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload; + socbridge_driver_to_ip.is_full_out <= '0'; end if; when TX_BODY => if st.write_stage > 0 then - socbridge_driver_to_buffer.is_full_out <= '0'; - socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload; + socbridge_driver_to_ip.is_full_out <= '0'; + socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload; else socbridge_driver_to_ext_data_cmd := (others => '0'); end if; @@ -226,8 +226,8 @@ begin end if; when RX_RESPONSE => when RX_BODY => - socbridge_driver_to_buffer.payload <= st.ext_to_socbridge_driver_reg.data; - socbridge_driver_to_buffer.write_enable_in <= '1'; + socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data; + socbridge_driver_to_ip.write_enable_in <= '1'; when ADDR1 => socbridge_driver_to_ext_data_cmd := st.curr_addr(15 downto 8); when ADDR2 => @@ -236,9 +236,9 @@ begin socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24); when ADDR4 => if st.curr_cmd = WRITE_ADD then - socbridge_driver_to_buffer.is_full_out <= '0'; - socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload; - report integer'image(to_integer(signed(socbridge_driver_to_ext_data_cmd))) & " "& integer'image(to_integer(signed(buffer_to_socbridge_driver.payload))); + socbridge_driver_to_ip.is_full_out <= '0'; + socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload; + report integer'image(to_integer(signed(socbridge_driver_to_ext_data_cmd))) & " "& integer'image(to_integer(signed(ip_to_socbridge_driver.payload))); end if; end case; next_parity_out <= calc_parity(socbridge_driver_to_ext_data_cmd); diff --git a/src/socbridge/socbridge_driver_tb.vhd b/src/socbridge/socbridge_driver_tb.vhd index 0471486..2f77720 100644 --- a/src/socbridge/socbridge_driver_tb.vhd +++ b/src/socbridge/socbridge_driver_tb.vhd @@ -19,8 +19,8 @@ architecture tb of socbridge_driver_tb is signal cmd_size : positive; signal ext_to_socbridge_driver : ext_to_socbridge_driver_t; signal socbridge_driver_to_ext : socbridge_driver_to_ext_t; - signal buffer_to_socbridge_driver : buffer_to_socbridge_driver_t; - signal socbridge_driver_to_buffer : socbridge_driver_to_buffer_t; + signal ip_to_socbridge_driver : ip_to_socbridge_driver_t; + signal socbridge_driver_to_ip : socbridge_driver_to_ip_t; signal controller_to_socbridge_driver : controller_to_socbridge_driver_t; signal socbridge_driver_controller : socbridge_driver_to_controller_t; signal curr_word : std_logic_vector(ext_to_socbridge_driver.payload'length - 1 downto 0); @@ -71,8 +71,8 @@ architecture tb of socbridge_driver_tb is -- cmd_size: in positive; -- ext_to_socbridge_driver : in ext_to_socbridge_driver_t; -- socbridge_driver_to_ext : out socbridge_driver_to_ext_t; --- buffer_to_socbridge_driver : out buffer_to_socbridge_driver_t; --- socbridge_driver_to_buffer : in socbridge_driver_to_buffer_t +-- ip_to_socbridge_driver : out ip_to_socbridge_driver_t; +-- socbridge_driver_to_ip : in socbridge_driver_to_ip_t -- ); -- end component socbridge_driver; @@ -85,8 +85,8 @@ begin socbridge_driver_to_controller => socbridge_driver_controller, ext_to_socbridge_driver => ext_to_socbridge_driver, socbridge_driver_to_ext => socbridge_driver_to_ext, - buffer_to_socbridge_driver => buffer_to_socbridge_driver, - socbridge_driver_to_buffer => socbridge_driver_to_buffer + ip_to_socbridge_driver => ip_to_socbridge_driver, + socbridge_driver_to_ip => socbridge_driver_to_ip ); ext_to_socbridge_driver.control(1) <= clk; @@ -299,30 +299,30 @@ begin internal_stimulus: process begin - buffer_to_socbridge_driver.is_full_in <= '0'; - buffer_to_socbridge_driver.write_enable_out <= '0'; + ip_to_socbridge_driver.is_full_in <= '0'; + ip_to_socbridge_driver.write_enable_out <= '0'; wait for 3 * CLK_PERIOD; -- stimulus goes here - buffer_to_socbridge_driver.write_enable_out <= '1'; - buffer_to_socbridge_driver.payload <= "00000001"; - wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0'; + ip_to_socbridge_driver.write_enable_out <= '1'; + ip_to_socbridge_driver.payload <= "00000001"; + wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0'; wait until falling_edge(clk); - buffer_to_socbridge_driver.payload <= "00000010"; - wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0'; + ip_to_socbridge_driver.payload <= "00000010"; + wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0'; wait until falling_edge(clk); - buffer_to_socbridge_driver.payload <= "00000100"; - wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0'; + ip_to_socbridge_driver.payload <= "00000100"; + wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0'; wait until falling_edge(clk); - buffer_to_socbridge_driver.payload <= "00001000"; - wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0'; + ip_to_socbridge_driver.payload <= "00001000"; + wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0'; wait until falling_edge(clk); - buffer_to_socbridge_driver.payload <= "00010000"; - wait until socbridge_driver_to_buffer.is_full_out = '0'; + ip_to_socbridge_driver.payload <= "00010000"; + wait until socbridge_driver_to_ip.is_full_out = '0'; wait for CLK_PERIOD/2; wait until rising_edge(clk); wait until rising_edge(clk); - buffer_to_socbridge_driver.payload <= "00100000"; - wait until socbridge_driver_to_buffer.is_full_out = '0'; + ip_to_socbridge_driver.payload <= "00100000"; + wait until socbridge_driver_to_ip.is_full_out = '0'; wait for CLK_PERIOD/2; wait until rising_edge(clk); wait until rising_edge(clk); --- ??? Why all these rising_edge checks? diff --git a/src/socbridge/socbridge_driver_tb_pkg.vhd b/src/socbridge/socbridge_driver_tb_pkg.vhd index fc8e8cd..be1b981 100644 --- a/src/socbridge/socbridge_driver_tb_pkg.vhd +++ b/src/socbridge/socbridge_driver_tb_pkg.vhd @@ -27,7 +27,7 @@ package socbridge_driver_tb_pkg is curr_inst : controller_to_socbridge_driver_t; curr_state : translator_state_t; is_first_word : std_logic; - end record translator_state_rec_t; + end record translator_state_rec_t; type ext_protocol_t is record data : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0); diff --git a/src/vhdl_ls.toml b/src/vhdl_ls.toml index 3a01a68..6699650 100644 --- a/src/vhdl_ls.toml +++ b/src/vhdl_ls.toml @@ -3,7 +3,8 @@ standard = "1993" # File names are either absolute or relative to the parent folder of the vhdl_ls.toml file [libraries] ganimede.files = [ - 'ganimede/io_type_pkg.vhd' + 'ganimede/io_type_pkg.vhd', + 'ganimede/ganimede.vhd' ] socbridge.files = [ 'socbridge/*.vhd'