Started working on io for control unit
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src/control_unit.vhd
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34
src/control_unit.vhd
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@ -0,0 +1,34 @@
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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library work;
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use work.io_types.all;
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entity control_unit is
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port (
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clk, rst: in std_logic;
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address_read_in, address_write_in: in control_unit_ext_t.address;
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address_read_out, address_write_out: in control_unit_ext_t.address);
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words_to_read_in: in std_logic_vector(control_unit_ext_t.seq_read_count);
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words_to_write_in: in std_logic_vector(control_unit_ext_t.seq_write_count);
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);
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end entity control_unit;
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architecture behave of control_unit is
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begin
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main_proc: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '0' then
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else
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end if;
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end if;
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end process main_proc;
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end architecture behave;
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@ -15,6 +15,15 @@ package io_types is
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socbridge: ext_protocol_def_t;
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end record interface_inst_t;
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constant number_of_drivers = 3;
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type control_unit_ext_t is record
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interface_id_count: in std_logic_vector(number_of_drivers)) downto 0);
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address: in std_logic_vector(32 downto 0);
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seq_write_count: in std_logic_vector(7 downto 0);
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seq_read_count: in std_logic_vector(7 downto 0);
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end record control_unit_format;
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--- PROTOCOL INFORMATION ---
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constant interface_inst : interface_inst_t := (
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socbridge => ("SoCBridge ", 8, 2, 2)
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