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Fixed a read-write mixup

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Adam 2025-04-22 19:43:26 +02:00
parent 15ea79bed6
commit 8db176c6b5
2 changed files with 4 additions and 3 deletions
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3
src/fifo_buffer/fifo_buffer.vhd
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@ -53,7 +53,8 @@ begin
techmap_ram_inst : entity techmap.syncram_2p techmap_ram_inst : entity techmap.syncram_2p
generic map(tech => tech, generic map(tech => tech,
abits => address_bits, abits => address_bits,
dbits => fifo_width dbits => fifo_width,
sepclk => 1
) )
port map( port map(
rclk => out_clk, rclk => out_clk,

4
src/manager/management_unit.vhd
View File

@ -76,9 +76,9 @@ begin
-- CLEAR BUFFER TO IP CORE -- CLEAR BUFFER TO IP CORE
end if; end if;
-- Is the controller done executing an instruction -- Is the controller done executing an instruction
elsif controller_to_manager.done = '1' and cmd = "01" then
manager_state.memory(0) <= manager_word_reset_val;
elsif controller_to_manager.done = '1' and cmd = "10" then elsif controller_to_manager.done = '1' and cmd = "10" then
manager_state.memory(0) <= manager_word_reset_val;
elsif controller_to_manager.done = '1' and cmd = "01" then
manager_state.memory(1) <= manager_word_reset_val; manager_state.memory(1) <= manager_word_reset_val;
end if; end if;
-- Is there a read instruction in memory -- Is there a read instruction in memory