Fixed a read-write mixup

src/fifo_buffer/fifo_buffer.vhd

@@ -53,7 +53,8 @@ begin
   techmap_ram_inst : entity techmap.syncram_2p
   generic map(tech => tech, 
               abits => address_bits, 
-              dbits => fifo_width
+              dbits => fifo_width,
+              sepclk => 1
              )
   port map(
     rclk     => out_clk,

src/manager/management_unit.vhd

@@ -76,9 +76,9 @@ begin
           -- CLEAR BUFFER TO IP CORE
         end if;
       -- Is the controller done executing an instruction
-      elsif controller_to_manager.done = '1' and cmd = "01" then
-        manager_state.memory(0) <= manager_word_reset_val;
       elsif controller_to_manager.done = '1' and cmd = "10" then
+        manager_state.memory(0) <= manager_word_reset_val;
+      elsif controller_to_manager.done = '1' and cmd = "01" then
         manager_state.memory(1) <= manager_word_reset_val;
       end if;
       -- Is there a read instruction in memory