diff --git a/src/ganimede/ganimede.vhd b/src/ganimede/ganimede.vhd index 26592a1..66e8d75 100644 --- a/src/ganimede/ganimede.vhd +++ b/src/ganimede/ganimede.vhd @@ -29,6 +29,7 @@ architecture rtl of ganimede_toplevel is signal manager_to_socbridge_driver : manager_to_socbridge_driver_t; signal socbridge_driver_to_buffer : fifo_interface_t; signal buffer_to_socbridge_driver : fifo_interface_t; + signal ip_to_socbridge_driver : ip_to_socbridge_driver_t; signal socbridge_clk : std_logic; --signal gan_socbridge_WE_in : std_logic; @@ -37,7 +38,9 @@ architecture rtl of ganimede_toplevel is --signal gan_socbridge_is_full_out : std_logic; begin - --- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS --- + --- INTERNAL CONNECTIONS --- + ip_to_socbridge_driver.fifo <= buffer_to_socbridge_driver; + ip_to_socbridge_driver.flush <= ip_to_ganimede.socbridge.flush; --- DRIVER INSTANTIATION --- socbridge_driver_inst: entity gan_socbridge.socbridge_driver @@ -51,7 +54,7 @@ begin socbridge_driver_to_manager => socbridge_driver_to_manager, ext_to_socbridge_driver => ext_to_ganimede.socbridge, socbridge_driver_to_ext => ganimede_to_ext.socbridge, - ip_to_socbridge_driver => buffer_to_socbridge_driver, + ip_to_socbridge_driver => ip_to_socbridge_driver, socbridge_driver_to_ip => socbridge_driver_to_buffer ); @@ -84,7 +87,7 @@ begin in_clk => socbridge_clk, out_clk => clk, rst => rst, - ready_in => ip_to_ganimede.socbridge.ready, + ready_in => ip_to_ganimede.socbridge.fifo.ready, ready_out => buffer_to_socbridge_driver.ready, valid_in => socbridge_driver_to_buffer.valid, valid_out => ganimede_to_ip.socbridge.valid, @@ -103,14 +106,12 @@ begin rst => rst, ready_in => socbridge_driver_to_buffer.ready, ready_out => ganimede_to_ip.socbridge.ready, - valid_in => ip_to_ganimede.socbridge.valid, + valid_in => ip_to_ganimede.socbridge.fifo.valid, valid_out => buffer_to_socbridge_driver.valid, - data_in => ip_to_ganimede.socbridge.data, + data_in => ip_to_ganimede.socbridge.fifo.data, data_out => buffer_to_socbridge_driver.data, used_slots => buffer_to_socbridge_driver.used_slots ); - --- LATER WE ADD OPTIMIZATIONS HERE --- - end architecture rtl; diff --git a/src/ganimede/io_type_pkg.vhd b/src/ganimede/io_type_pkg.vhd index e1d070c..c9e000f 100644 --- a/src/ganimede/io_type_pkg.vhd +++ b/src/ganimede/io_type_pkg.vhd @@ -71,7 +71,10 @@ package io_types is subtype socbridge_driver_to_ip_t is fifo_interface_t; - subtype ip_to_socbridge_driver_t is fifo_interface_t; + type ip_to_socbridge_driver_t is record + fifo: fifo_interface_t; + flush: std_logic; + end record ip_to_socbridge_driver_t; type controller_to_drivers_t is record socbridge : controller_to_socbridge_driver_t; diff --git a/src/manager/management_unit.vhd b/src/manager/management_unit.vhd index caed8da..9b8d46f 100644 --- a/src/manager/management_unit.vhd +++ b/src/manager/management_unit.vhd @@ -76,10 +76,13 @@ begin -- CLEAR BUFFER TO IP CORE end if; -- Is the controller done executing an instruction - elsif controller_to_manager.done_reading = '1' then - manager_state.memory(0) <= manager_word_reset_val; - elsif controller_to_manager.done_writing = '1' then - manager_state.memory(1) <= manager_word_reset_val; + else + if controller_to_manager.done_reading = '1' then + manager_state.memory(0) <= manager_word_reset_val; + end if; + if controller_to_manager.done_writing = '1' then + manager_state.memory(1) <= manager_word_reset_val; + end if; end if; -- Is there a read instruction in memory if pack(read_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then diff --git a/src/socbridge/socbridge_driver.vhd b/src/socbridge/socbridge_driver.vhd index 845089f..ef5e904 100644 --- a/src/socbridge/socbridge_driver.vhd +++ b/src/socbridge/socbridge_driver.vhd @@ -238,8 +238,8 @@ begin when TX_W_BODY => if st.tx_stage > 0 then socbridge_driver_to_ip.ready <= '1'; - if ip_to_socbridge_driver.valid = '1' then - local_next_data_out := ip_to_socbridge_driver.data; + if ip_to_socbridge_driver.fifo.valid = '1' then + local_next_data_out := ip_to_socbridge_driver.fifo.data; else local_next_data_out := (others => '0'); end if; @@ -293,7 +293,8 @@ begin if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD or st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then trans_write_next_state <= IDLE; - elsif trans_st.write.curr_inst.request = '1' then + elsif trans_st.write.curr_inst.request = '1' and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE + or ip_to_socbridge_driver.flush = '1') then trans_write_next_state <= SEND; else trans_write_next_state <= IDLE; @@ -312,7 +313,11 @@ begin when AWAIT => if trans_st.write.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then trans_write_next_state <= IDLE; - elsif st.curr_tx_state = IDLE then + elsif ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1' + and st.curr_tx_state = IDLE then + trans_write_next_state <= IDLE; + elsif st.curr_tx_state = IDLE and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE + or ip_to_socbridge_driver.flush = '1') then trans_write_next_state <= SEND; else trans_write_next_state <= AWAIT; @@ -345,6 +350,8 @@ begin when AWAIT => if trans_st.read.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then trans_read_next_state <= IDLE; + elsif ip_to_socbridge_driver.flush = '1'and st.curr_tx_state = IDLE then + trans_read_next_state <= IDLE; elsif st.curr_tx_state = IDLE then trans_read_next_state <= SEND; else @@ -543,7 +550,9 @@ begin trans_st.write.curr_inst.seq_mem_access_count <= trans_st.write.curr_inst.seq_mem_access_count - MAX_PKT_SIZE; trans_st.write.curr_inst.address <= std_logic_vector(unsigned(trans_st.write.curr_inst.address) + MAX_PKT_SIZE); when AWAIT => - if trans_st.write.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then + if ((ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1') + or trans_st.write.curr_inst.seq_mem_access_count <= 0) + and st.curr_tx_state = TX_W_BODY then trans_st.write.curr_inst.request <= '0'; trans_st.write.curr_inst.address <= (others => '0'); trans_st.write.curr_inst.seq_mem_access_count <= 0; @@ -570,7 +579,7 @@ begin trans_st.read.curr_inst.seq_mem_access_count <= trans_st.read.curr_inst.seq_mem_access_count - MAX_PKT_SIZE; trans_st.read.curr_inst.address <= std_logic_vector(unsigned(trans_st.read.curr_inst.address) + MAX_PKT_SIZE); when AWAIT => - if trans_st.read.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then + if (ip_to_socbridge_driver.flush = '1' or trans_st.read.curr_inst.seq_mem_access_count <= 0) and st.curr_tx_state = IDLE then trans_st.read.curr_inst.request <= '0'; trans_st.read.curr_inst.address <= (others => '0'); trans_st.read.curr_inst.seq_mem_access_count <= 0;