added dummy ip core which increments each element by 1

src/dummy_ip/dummy_ip.vhd

@@ -0,0 +1,44 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity dummy_ip is
+  generic (
+    data_width : natural := 8
+  );
+  port (
+    clk, rst : in std_logic;
+    ready_in, valid_in : in std_logic;
+    ready_out, valid_out : out std_logic;
+    data_in : in std_logic_vector(data_width - 1 downto 0);
+    data_out : out std_logic_vector(data_width - 1 downto 0)
+  );
+end entity dummy_ip;
+
+architecture rtl of dummy_ip is
+  signal incremented_in : std_logic_vector(data_width - 1 downto 0);
+  signal valid_out_signal : std_logic;
+begin
+ 
+valid_out <= valid_out_signal;
+data_out  <= incremented_in;  
+
+seq_proc: process(clk, data_in, ready_in, valid_in)
+begin
+  if rst = '1' then
+    incremented_in <= (others => '0');
+    valid_out_signal <= '0';
+    ready_out <= '1';
+  else
+    if falling_edge(clk) and valid_in = '1'then
+      incremented_in <= std_logic_vector(unsigned(data_in) + 1);    
+      valid_out_signal <= '1';
+      ready_out <= '0';
+    elsif rising_edge(clk) and valid_out_signal = '1' and ready_in = '1' then
+      valid_out_signal <= '0';
+      ready_out <= '1';
+    end if;
+  end if;
+end process seq_proc;
+  
+end architecture rtl;

src/gantry.toml

@@ -20,6 +20,10 @@ path = "ganimede"
 vhdl-version = "93c"
 path = "controller"
 
+[libraries.gan_dummy_ip]
+vhdl-version = "93c"
+path = "dummy_ip"
+
 [libraries.gan_testbenches]
 vhdl-version = "93c"
 path = "control_socbridge_merge"

src/vhdl_ls.toml

@@ -9,7 +9,9 @@ gan_ganimede.files = [
 gan_socbridge.files = [
     'socbridge/*.vhd'
 ]
-
+gan_dummy_ip.files = [
+    'dummy_ip/*.vhd'
+]
 gan_controller.files = [
     'controller/*.vhd',
 ]