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cleanup: reduced manager signals kept in state furhter (no io pipelining support for external users) and removed valid and data_out stateful assignment

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This commit is contained in:
Erik Örtenberg 2025-05-23 16:36:07 +02:00
parent 5f9783f3b3
commit 9cdcb8cd74
2 changed files with 15 additions and 24 deletions
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34
src/socbridge/socbridge_driver.vhd
View File

@ -42,13 +42,11 @@ architecture rtl of socbridge_driver is
signal next_rx_state : rx_state_t; signal next_rx_state : rx_state_t;
signal next_tx_state : tx_state_t; signal next_tx_state : tx_state_t;
signal st : state_rec_t; signal st : state_rec_t;
signal valid_out : std_logic;
--- TRANSLATOR --- --- TRANSLATOR ---
signal trans_st : translator_state_t; signal trans_st : translator_state_t;
signal trans_read_next_state : ctrl_inst_state_t; signal trans_read_next_state : ctrl_inst_state_t;
signal trans_write_next_state : ctrl_inst_state_t; signal trans_write_next_state : ctrl_inst_state_t;
--- FSM COMMUNICATION --- --- FSM COMMUNICATION ---
signal tx_sent_response, rx_received_response : std_logic;
--- MANAGEMENT COMMUNICATION --- --- MANAGEMENT COMMUNICATION ---
begin begin
ext_to_socbridge_driver_rec.data <= ext_to_socbridge_driver.payload; ext_to_socbridge_driver_rec.data <= ext_to_socbridge_driver.payload;
@ -56,10 +54,8 @@ begin
ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0); ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0);
socbridge_clk <= ext_to_socbridge_driver_rec.clk; socbridge_clk <= ext_to_socbridge_driver_rec.clk;
comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver, comb_proc: process(ext_to_socbridge_driver_rec, ip_to_socbridge_driver,
st, controller_to_socbridge_driver, trans_st, controller_to_socbridge_driver, st, trans_st)
tx_sent_response, rx_received_response,
valid_out)
variable curr_response_bits : std_logic_vector(4 downto 0); variable curr_response_bits : std_logic_vector(4 downto 0);
variable local_next_rx_transaction : transaction_t; variable local_next_rx_transaction : transaction_t;
variable local_next_tx_transaction : transaction_t; variable local_next_tx_transaction : transaction_t;
@ -67,8 +63,8 @@ begin
begin begin
-- DEFAULT VALUES -- DEFAULT VALUES
-- Helpful Bindings -- -- Helpful Bindings --
next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver.payload(2 downto 0))); next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver_rec.data(2 downto 0)));
curr_response_bits := ext_to_socbridge_driver.payload(7 downto 3); curr_response_bits := ext_to_socbridge_driver_rec.data(7 downto 3);
-- Set helper var to current transaction seen at the input. -- Set helper var to current transaction seen at the input.
local_next_rx_transaction := NO_OP; local_next_rx_transaction := NO_OP;
if curr_response_bits = "10000" then if curr_response_bits = "10000" then
@ -262,7 +258,7 @@ begin
end if; end if;
when TX_R_BODY => when TX_R_BODY =>
if st.tx_stage > 0 then if st.tx_stage > 0 then
local_next_data_out := st.curr_read_data((((st.tx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.tx_stage - 1) mod 4) + 1) - 1) * 8); local_next_data_out := st.manager_data((((st.tx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.tx_stage - 1) mod 4) + 1) - 1) * 8);
end if; end if;
when TX_AWAIT => when TX_AWAIT =>
when ADDR1 => when ADDR1 =>
@ -281,19 +277,22 @@ begin
socbridge_driver_to_manager.valid <= '0'; socbridge_driver_to_manager.valid <= '0';
socbridge_driver_to_manager.address <= (others => '0'); socbridge_driver_to_manager.address <= (others => '0');
socbridge_driver_to_manager.data <= (others => '0'); socbridge_driver_to_manager.data <= (others => '0');
socbridge_driver_to_ip.valid <= '0';
socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
case st.curr_rx_state is case st.curr_rx_state is
when IDLE => when IDLE =>
when RX_HEADER => when RX_HEADER =>
when RX_W_BODY => when RX_W_BODY =>
if st.rx_stage mod 4 = 0 and st.rx_stage /= st.rx_data_size then if st.rx_stage mod 4 = 0 and st.rx_stage /= st.rx_data_size then
socbridge_driver_to_manager.data <= st.curr_write_data; socbridge_driver_to_manager.data <= st.manager_data;
socbridge_driver_to_manager.address <= st.manager_addr; socbridge_driver_to_manager.address <= st.manager_addr;
socbridge_driver_to_manager.valid <= '1'; socbridge_driver_to_manager.valid <= '1';
end if; end if;
when RX_R_BODY => when RX_R_BODY =>
socbridge_driver_to_ip.valid <= '1';
when RX_AWAIT => when RX_AWAIT =>
if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
socbridge_driver_to_manager.data <= st.curr_write_data; socbridge_driver_to_manager.data <= st.manager_data;
socbridge_driver_to_manager.address <= st.manager_addr; socbridge_driver_to_manager.address <= st.manager_addr;
socbridge_driver_to_manager.valid <= '1'; socbridge_driver_to_manager.valid <= '1';
else else
@ -420,7 +419,6 @@ begin
next_tx_transaction <= local_next_tx_transaction; next_tx_transaction <= local_next_tx_transaction;
next_rx_transaction <= local_next_rx_transaction; next_rx_transaction <= local_next_rx_transaction;
next_data_out <= local_next_data_out; next_data_out <= local_next_data_out;
socbridge_driver_to_ip.valid <= valid_out;
end process comb_proc; end process comb_proc;
-- Process updating internal registers based on primary clock -- Process updating internal registers based on primary clock
seq_proc: process(ext_to_socbridge_driver_rec.clk, st.ext_to_socbridge_driver_reg.data, rst, clk) seq_proc: process(ext_to_socbridge_driver_rec.clk, st.ext_to_socbridge_driver_reg.data, rst, clk)
@ -439,13 +437,10 @@ begin
st.tx_data_size <= 0; st.tx_data_size <= 0;
st.rx_data_size <= 0; st.rx_data_size <= 0;
st.manager_addr <= (others => '0'); st.manager_addr <= (others => '0');
st.curr_write_data <= (others => '0'); st.manager_data <= (others => '0');
st.curr_read_data <= (others => '0');
socbridge_driver_to_ip.data <= (others => '0');
st.read_in_flight <= false; st.read_in_flight <= false;
st.write_in_flight <= false; st.write_in_flight <= false;
st.last_sent_transaction <= NO_OP; st.last_sent_transaction <= NO_OP;
valid_out <= '0';
elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data; st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data;
@ -456,7 +451,6 @@ begin
st.socbridge_driver_to_ext_reg.parity <= next_parity_out; st.socbridge_driver_to_ext_reg.parity <= next_parity_out;
st.curr_tx_state <= next_tx_state; st.curr_tx_state <= next_tx_state;
st.curr_rx_state <= next_rx_state; st.curr_rx_state <= next_rx_state;
valid_out <= '0';
case st.curr_tx_state is case st.curr_tx_state is
when IDLE => when IDLE =>
if ip_to_socbridge_driver.flush = '1' then if ip_to_socbridge_driver.flush = '1' then
@ -536,8 +530,6 @@ begin
end if; end if;
end if; end if;
when RX_R_BODY => when RX_R_BODY =>
valid_out <= '1';
socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
if st.rx_stage > 0 then if st.rx_stage > 0 then
st.rx_stage <= st.rx_stage - 1; st.rx_stage <= st.rx_stage - 1;
end if; end if;
@ -554,13 +546,13 @@ begin
when RX_W_BODY => when RX_W_BODY =>
if st.rx_stage > 0 then if st.rx_stage > 0 then
st.rx_stage <= st.rx_stage - 1; st.rx_stage <= st.rx_stage - 1;
st.curr_write_data((((st.rx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.rx_stage - 1) mod 4) + 1) - 1) * 8) <= st.ext_to_socbridge_driver_reg.data; st.manager_data((((st.rx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.rx_stage - 1) mod 4) + 1) - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
end if; end if;
if (st.rx_stage - 2) mod 4 = 0 and st.rx_data_size - st.rx_stage > 4 then if (st.rx_stage - 2) mod 4 = 0 and st.rx_data_size - st.rx_stage > 4 then
st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32)); st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
end if; end if;
when RX_AWAIT => when RX_AWAIT =>
st.curr_read_data <= manager_to_socbridge_driver.data; st.manager_data <= manager_to_socbridge_driver.data;
-- THIS DOESN'T WORK FOR LARGER THAN 4 BYTE ACCESSES, SHOULD BE FIXED BUT NOT NEEDED IF ONLY 4 BYTE ACCESSES ARRIVE -- THIS DOESN'T WORK FOR LARGER THAN 4 BYTE ACCESSES, SHOULD BE FIXED BUT NOT NEEDED IF ONLY 4 BYTE ACCESSES ARRIVE
if st.curr_tx_transaction = READ_RESPONSE or st.curr_tx_transaction = WRITE_ACK then if st.curr_tx_transaction = READ_RESPONSE or st.curr_tx_transaction = WRITE_ACK then
if (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then if (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then

5
src/socbridge/socbridge_driver_pkg.vhd
View File

@ -55,13 +55,12 @@ package socbridge_driver_pkg is
ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t; ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t;
tx_stage, rx_stage : NATURAL; tx_stage, rx_stage : NATURAL;
tx_data_size, rx_data_size : integer; tx_data_size, rx_data_size : integer;
curr_write_data : std_logic_vector(31 downto 0);
curr_read_data : std_logic_vector(31 downto 0);
curr_tx_addr : std_logic_vector(31 downto 0); curr_tx_addr : std_logic_vector(31 downto 0);
manager_addr : std_logic_vector(31 downto 0);
read_in_flight : boolean; read_in_flight : boolean;
write_in_flight : boolean; write_in_flight : boolean;
last_sent_transaction : transaction_t; last_sent_transaction : transaction_t;
manager_addr : std_logic_vector(31 downto 0);
manager_data : std_logic_vector(31 downto 0);
end record state_rec_t; end record state_rec_t;
impure function calc_parity( impure function calc_parity(
d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0) d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)