fixed reading/writing from/to socbridge in entire system
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48dff427d4
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a656eb24e7
@ -34,7 +34,7 @@ write_address <= manager_state.memory(1);
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comb_proc: process(controller_to_manager, socbridge_driver_to_manager,manager_state)
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comb_proc: process(controller_to_manager, socbridge_driver_to_manager,manager_state)
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variable local_word_address : natural;
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variable local_word_address : natural;
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begin
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begin
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local_word_address := to_integer(shift_right(unsigned(socbridge_driver_to_manager.address), address_shift));
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local_word_address := to_integer(shift_right(unsigned(socbridge_driver_to_manager.address and address_mask), address_shift));
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-- Read data from manager to SoCBridge driver
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-- Read data from manager to SoCBridge driver
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manager_to_socbridge_driver.ready <= '1';
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manager_to_socbridge_driver.ready <= '1';
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manager_to_socbridge_driver.data <= manager_state.memory(local_word_address);
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manager_to_socbridge_driver.data <= manager_state.memory(local_word_address);
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@ -1,5 +1,6 @@
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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use IEEE.MATH_REAL.all;
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use IEEE.MATH_REAL.all;
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library gan_ganimede;
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library gan_ganimede;
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use gan_ganimede.io_types.all;
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use gan_ganimede.io_types.all;
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@ -11,6 +12,7 @@ package management_types is
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subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0);
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subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0);
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constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
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constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
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constant mem_words : natural := 64;
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constant mem_words : natural := 64;
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constant address_mask : std_logic_vector(WORD_SIZE - 1 downto 0) := std_logic_vector(to_unsigned(mem_words - 1, 32));
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type memory_t is array (0 to mem_words - 1) of manager_word_t;
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type memory_t is array (0 to mem_words - 1) of manager_word_t;
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-- Index in memory array where memory read address is kept.
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-- Index in memory array where memory read address is kept.
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@ -231,7 +231,7 @@ begin
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end if;
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end if;
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when TX_R_BODY =>
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when TX_R_BODY =>
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if st.tx_stage > 0 then
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if st.tx_stage > 0 then
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local_next_data_out := st.curr_read_data(st.tx_stage * 8 - 1 downto (st.tx_stage - 1) * 8);
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local_next_data_out := st.curr_read_data((((st.tx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.tx_stage - 1) mod 4) + 1) - 1) * 8);
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end if;
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end if;
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when TX_AWAIT =>
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when TX_AWAIT =>
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when ADDR1 =>
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when ADDR1 =>
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@ -414,18 +414,18 @@ begin
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when RX_W_BODY =>
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when RX_W_BODY =>
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if st.rx_stage > 0 then
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if st.rx_stage > 0 then
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st.rx_stage <= st.rx_stage - 1;
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st.rx_stage <= st.rx_stage - 1;
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st.curr_write_data((st.rx_stage) * 8 - 1 downto (st.rx_stage - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
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st.curr_write_data((((st.rx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.rx_stage - 1) mod 4) + 1) - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
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end if;
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end if;
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when RX_AWAIT =>
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when RX_AWAIT =>
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st.curr_read_data <= manager_to_socbridge_driver.data;
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st.curr_read_data <= manager_to_socbridge_driver.data;
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-- THIS DOESN'T WORK, SHOULD BE FIXED BUT NOT NEEDED IF ONLY 4 BYTE ACCESSES ARRIVE
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-- THIS DOESN'T WORK FOR LARGER THAN 4 BYTE ACCESSES, SHOULD BE FIXED BUT NOT NEEDED IF ONLY 4 BYTE ACCESSES ARRIVE
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--if st.curr_tx_transaction = READ_RESPONSE or st.curr_tx_transaction = WRITE_ACK then
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if st.curr_tx_transaction = READ_RESPONSE or st.curr_tx_transaction = WRITE_ACK then
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-- if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD then
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if (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then
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-- st.curr_rx_read_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_read_addr) + 4), 32));
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st.curr_rx_read_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_read_addr) + 4), 32));
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-- elsif st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
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elsif (st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD) and (st.rx_stage - 2) mod 4 = 0 then
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-- st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_read_addr) + 4), 32));
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st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32));
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-- end if;
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end if;
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--end if;
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end if;
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when ADDR1 =>
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when ADDR1 =>
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if st.curr_rx_transaction = READ_ADD then
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if st.curr_rx_transaction = READ_ADD then
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st.curr_rx_read_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
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st.curr_rx_read_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
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