From a84397d6265b2987d46af244153982ade5f6088d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Erik=20=C3=96rtenberg?= Date: Fri, 23 May 2025 17:08:58 +0200 Subject: [PATCH] cleanup: renamed variables to simplify. --- src/socbridge/socbridge_driver.vhd | 259 +++++++++++-------------- src/socbridge/socbridge_driver_pkg.vhd | 61 +++++- 2 files changed, 164 insertions(+), 156 deletions(-) diff --git a/src/socbridge/socbridge_driver.vhd b/src/socbridge/socbridge_driver.vhd index 4420c85..c2fcdd1 100644 --- a/src/socbridge/socbridge_driver.vhd +++ b/src/socbridge/socbridge_driver.vhd @@ -86,12 +86,12 @@ begin socbridge_driver_to_ext.payload <= st.socbridge_driver_to_ext_reg.data; socbridge_driver_to_ext.control(0) <= st.socbridge_driver_to_ext_reg.parity; socbridge_driver_to_ext.control(1) <= st.socbridge_driver_to_ext_reg.clk; - if trans_st.read.curr_state = IDLE then + if trans_st.read.state = IDLE then socbridge_driver_to_controller.is_reading <= '0'; else socbridge_driver_to_controller.is_reading <= '1'; end if; - if trans_st.write.curr_state = IDLE then + if trans_st.write.state = IDLE then socbridge_driver_to_controller.is_writing <= '0'; else socbridge_driver_to_controller.is_writing <= '1'; @@ -99,7 +99,7 @@ begin --- Next State Assignments --- --- ### TX NEXT STATE ASSIGNMENTS ### --- - case st.curr_tx_state is + case st.tx_state is when IDLE => if (local_next_tx_transaction = WRITE or local_next_tx_transaction = WRITE_ADD) and not st.write_in_flight then next_tx_state <= TX_HEADER; @@ -112,14 +112,14 @@ begin end if; when TX_HEADER => -- Commands - if st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = READ_ADD then + if st.tx_transaction = WRITE_ADD or st.tx_transaction = READ_ADD then next_tx_state <= ADDR1; - elsif st.curr_tx_transaction = WRITE then + elsif st.tx_transaction = WRITE then next_tx_state <= TX_W_BODY; - elsif st.curr_tx_transaction = READ then + elsif st.tx_transaction = READ then next_tx_state <= IDLE; -- Responses - elsif st.curr_tx_transaction = READ_RESPONSE then + elsif st.tx_transaction = READ_RESPONSE then next_tx_state <= TX_R_BODY; else next_tx_state <= IDLE; @@ -137,9 +137,9 @@ begin when ADDR3 => next_tx_state <= ADDR4; when ADDR4 => - if st.curr_tx_transaction = READ_ADD then + if st.tx_transaction = READ_ADD then next_tx_state <= IDLE; - elsif st.curr_tx_transaction = WRITE_ADD then + elsif st.tx_transaction = WRITE_ADD then next_tx_state <= TX_W_BODY; else next_tx_state <= IDLE; @@ -152,7 +152,7 @@ begin end if; end case; --- Next State Assignment Of RX FSM --- - case st.curr_rx_state is + case st.rx_state is when IDLE => if local_next_rx_transaction /= NO_OP then next_rx_state <= RX_HEADER; @@ -161,14 +161,14 @@ begin end if; when RX_HEADER => -- Commands - if st.curr_rx_transaction = WRITE_ADD or st.curr_rx_transaction = READ_ADD then + if st.rx_transaction = WRITE_ADD or st.rx_transaction = READ_ADD then next_rx_state <= ADDR1; - elsif st.curr_rx_transaction = WRITE then + elsif st.rx_transaction = WRITE then next_rx_state <= RX_W_BODY; - elsif st.curr_rx_transaction = READ then + elsif st.rx_transaction = READ then next_rx_state <= RX_AWAIT; -- Responses - elsif st.curr_rx_transaction = READ_RESPONSE then + elsif st.rx_transaction = READ_RESPONSE then next_rx_state <= RX_R_BODY; elsif local_next_rx_transaction /= NO_OP then next_rx_state <= RX_HEADER; @@ -192,9 +192,9 @@ begin when ADDR3 => next_rx_state <= ADDR4; when ADDR4 => - if st.curr_rx_transaction = READ_ADD then + if st.rx_transaction = READ_ADD then next_rx_state <= RX_AWAIT; - elsif st.curr_rx_transaction = WRITE_ADD then + elsif st.rx_transaction = WRITE_ADD then next_rx_state <= RX_W_BODY; else next_rx_state <= IDLE; -- Potentially superfluous safety @@ -207,11 +207,11 @@ begin end if; when RX_AWAIT => -- Wait for TX FSM to send a response - if (st.curr_rx_transaction = WRITE_ADD or st.curr_rx_transaction = WRITE) - and st.curr_tx_transaction = WRITE_ACK then + if (st.rx_transaction = WRITE_ADD or st.rx_transaction = WRITE) + and st.tx_transaction = WRITE_ACK then next_rx_state <= IDLE; - elsif (st.curr_rx_transaction = READ_ADD or st.curr_rx_transaction = READ) - and st.curr_tx_transaction = READ_RESPONSE and st.tx_stage = 1 then + elsif (st.rx_transaction = READ_ADD or st.rx_transaction = READ) + and st.tx_transaction = READ_RESPONSE and st.tx_stage = 1 then next_rx_state <= IDLE; else next_rx_state <= RX_AWAIT; @@ -223,15 +223,15 @@ begin local_next_data_out := (others => '0'); socbridge_driver_to_ip.ready <= '0'; --- ### TX_STATE BASED OUTPUT ### --- - case st.curr_tx_state is + case st.tx_state is when IDLE => when TX_HEADER => - if st.curr_tx_transaction = WRITE_ACK or st.curr_tx_transaction = READ_RESPONSE then - local_next_data_out := get_header_bits(st.curr_tx_transaction, st.curr_rx_transaction) & get_size_bits(st.rx_data_size); + if st.tx_transaction = WRITE_ACK or st.tx_transaction = READ_RESPONSE then + local_next_data_out := get_header_bits(st.tx_transaction, st.rx_transaction) & get_size_bits(st.rx_data_size); else - local_next_data_out := get_header_bits(st.curr_tx_transaction, st.curr_rx_transaction) & get_size_bits(st.tx_data_size); + local_next_data_out := get_header_bits(st.tx_transaction, st.rx_transaction) & get_size_bits(st.tx_data_size); end if; - if st.curr_tx_transaction = WRITE then + if st.tx_transaction = WRITE then socbridge_driver_to_ip.ready <= '1'; end if; when TX_W_BODY => @@ -250,14 +250,14 @@ begin local_next_data_out := st.manager_data((((st.tx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.tx_stage - 1) mod 4) + 1) - 1) * 8); end if; when ADDR1 => - local_next_data_out := st.curr_tx_addr(31 downto 24); + local_next_data_out := st.tx_addr(31 downto 24); when ADDR2 => - local_next_data_out := st.curr_tx_addr(23 downto 16); + local_next_data_out := st.tx_addr(23 downto 16); when ADDR3 => - local_next_data_out := st.curr_tx_addr(15 downto 8); + local_next_data_out := st.tx_addr(15 downto 8); when ADDR4 => - local_next_data_out := st.curr_tx_addr(7 downto 0); - if st.curr_tx_transaction = WRITE_ADD then + local_next_data_out := st.tx_addr(7 downto 0); + if st.tx_transaction = WRITE_ADD then socbridge_driver_to_ip.ready <= '1'; end if; end case; @@ -267,9 +267,7 @@ begin socbridge_driver_to_manager.data <= (others => '0'); socbridge_driver_to_ip.valid <= '0'; socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data; - case st.curr_rx_state is - when IDLE => - when RX_HEADER => + case st.rx_state is when RX_W_BODY => if st.rx_stage mod 4 = 0 and st.rx_stage /= st.rx_data_size then socbridge_driver_to_manager.data <= st.manager_data; @@ -279,27 +277,24 @@ begin when RX_R_BODY => socbridge_driver_to_ip.valid <= '1'; when RX_AWAIT => - if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then + if st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then socbridge_driver_to_manager.data <= st.manager_data; socbridge_driver_to_manager.address <= st.manager_addr; socbridge_driver_to_manager.valid <= '1'; else socbridge_driver_to_manager.address <= st.manager_addr; end if; - when ADDR1 => - when ADDR2 => - when ADDR3 => - when ADDR4 => + when others => end case; next_parity_out <= calc_parity(local_next_data_out); --- TRANSLATOR --- --- Next state assignment - case trans_st.write.curr_state is + case trans_st.write.state is when IDLE => - if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD - or st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then + if st.rx_transaction = READ or st.rx_transaction = READ_ADD + or st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then trans_write_next_state <= IDLE; - elsif trans_st.write.curr_inst.request = '1' and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE + elsif trans_st.write.inst.request = '1' and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE or ip_to_socbridge_driver.flush = '1') then trans_write_next_state <= SEND; else @@ -307,7 +302,7 @@ begin end if; -- Wait for driver to go idle and send next instruction. Then enter AWAIT when SEND => - if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then + if st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD then trans_write_next_state <= SEND_ACCEPTED; else trans_write_next_state <= SEND; @@ -317,7 +312,7 @@ begin trans_write_next_state <= AWAIT; -- Wait for driver to finish current instruction, then reenter SEND when AWAIT => - if trans_st.write.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and not st.write_in_flight then + if trans_st.write.inst.access_count <= MAX_PKT_SIZE and not st.write_in_flight then trans_write_next_state <= IDLE; elsif ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1' and not st.write_in_flight then @@ -329,22 +324,22 @@ begin trans_write_next_state <= AWAIT; end if; end case; - case trans_st.read.curr_state is + case trans_st.read.state is when IDLE => if next_rx_transaction = READ or next_rx_transaction = READ_ADD or next_rx_transaction = WRITE or next_rx_transaction = WRITE_ADD then trans_read_next_state <= IDLE; - elsif st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD - or st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then + elsif st.rx_transaction = READ or st.rx_transaction = READ_ADD + or st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then trans_read_next_state <= IDLE; - elsif trans_st.read.curr_inst.request = '1' and BUFFER_SIZE - ip_to_socbridge_driver.read_fifo.used_slots > 2*MAX_PKT_SIZE then + elsif trans_st.read.inst.request = '1' and BUFFER_SIZE - ip_to_socbridge_driver.read_fifo.used_slots > 2*MAX_PKT_SIZE then trans_read_next_state <= SEND; else trans_read_next_state <= IDLE; end if; -- Wait for driver to go idle and send next instruction. Then enter AWAIT when SEND => - if st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD then + if st.tx_transaction = READ or st.tx_transaction = READ_ADD then trans_read_next_state <= SEND_ACCEPTED; else trans_read_next_state <= SEND; @@ -354,7 +349,7 @@ begin trans_read_next_state <= AWAIT; -- Wait for driver to finish current instruction, then reenter SEND when AWAIT => - if trans_st.read.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and not st.read_in_flight then + if trans_st.read.inst.access_count <= MAX_PKT_SIZE and not st.read_in_flight then trans_read_next_state <= IDLE; elsif ip_to_socbridge_driver.flush = '1'and not st.read_in_flight then trans_read_next_state <= IDLE; @@ -368,37 +363,37 @@ begin --- NEXT TX TRANSACTION --- local_next_tx_transaction := NO_OP; next_tx_data_size <= 0; - if trans_st.read.curr_state = IDLE and trans_st.write.curr_state = IDLE and st.curr_rx_state = RX_AWAIT then - if (st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD) and manager_to_socbridge_driver.ready = '1' then + if trans_st.read.state = IDLE and trans_st.write.state = IDLE and st.rx_state = RX_AWAIT then + if (st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD) and manager_to_socbridge_driver.ready = '1' then local_next_tx_transaction := WRITE_ACK; - elsif (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and manager_to_socbridge_driver.valid = '1' then + elsif (st.rx_transaction = READ or st.rx_transaction = READ_ADD) and manager_to_socbridge_driver.valid = '1' then next_tx_data_size <= st.rx_data_size; local_next_tx_transaction := READ_RESPONSE; end if; - elsif trans_st.read.curr_state = SEND - and not ((st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD) and trans_st.write.curr_state = SEND) then + elsif trans_st.read.state = SEND + and not ((st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD) and trans_st.write.state = SEND) then if trans_st.read.is_first_word = '1' then local_next_tx_transaction := READ_ADD; else local_next_tx_transaction := READ; end if; - if trans_st.read.curr_inst.seq_mem_access_count > MAX_PKT_SIZE then + if trans_st.read.inst.access_count > MAX_PKT_SIZE then next_tx_data_size <= MAX_PKT_SIZE; - elsif trans_st.read.curr_inst.seq_mem_access_count > 0 then - next_tx_data_size <= trans_st.read.curr_inst.seq_mem_access_count; + elsif trans_st.read.inst.access_count > 0 then + next_tx_data_size <= trans_st.read.inst.access_count; else next_tx_data_size <= 0; end if; - elsif trans_st.write.curr_state = SEND and not st.read_in_flight then + elsif trans_st.write.state = SEND and not st.read_in_flight then if trans_st.write.is_first_word = '1' then local_next_tx_transaction := WRITE_ADD; else local_next_tx_transaction := WRITE; end if; - if trans_st.write.curr_inst.seq_mem_access_count > MAX_PKT_SIZE then + if trans_st.write.inst.access_count > MAX_PKT_SIZE then next_tx_data_size <= MAX_PKT_SIZE; - elsif trans_st.write.curr_inst.seq_mem_access_count > 0 then - next_tx_data_size <= trans_st.write.curr_inst.seq_mem_access_count; + elsif trans_st.write.inst.access_count > 0 then + next_tx_data_size <= trans_st.write.inst.access_count; else next_tx_data_size <= 0; end if; @@ -412,24 +407,7 @@ begin seq_proc: process(ext_to_socbridge_driver_rec.clk, rst, clk) begin if(rst = '1') then - st.ext_to_socbridge_driver_reg.data <= (others => '0'); - st.socbridge_driver_to_ext_reg.data <= (others => '0'); - st.socbridge_driver_to_ext_reg.clk <= '0'; - st.socbridge_driver_to_ext_reg.parity <= '1'; - st.curr_tx_state <= IDLE; - st.curr_rx_state <= IDLE; - st.tx_stage <= 0; - st.rx_stage <= 0; - st.curr_tx_transaction <= NO_OP; - st.curr_rx_transaction <= NO_OP; - st.tx_data_size <= 0; - st.rx_data_size <= 0; - st.manager_addr <= (others => '0'); - st.manager_data <= (others => '0'); - st.read_in_flight <= false; - st.write_in_flight <= false; - st.last_sent_transaction <= NO_OP; - + st <= st_reset_vec; elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data; -- PARITY CHECK NOT IMPLEMENTED, REMOVING @@ -437,9 +415,9 @@ begin st.socbridge_driver_to_ext_reg.data <= next_data_out; st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk; st.socbridge_driver_to_ext_reg.parity <= next_parity_out; - st.curr_tx_state <= next_tx_state; - st.curr_rx_state <= next_rx_state; - case st.curr_tx_state is + st.tx_state <= next_tx_state; + st.rx_state <= next_rx_state; + case st.tx_state is when IDLE => if ip_to_socbridge_driver.flush = '1' then st.last_sent_transaction <= NO_OP; @@ -447,33 +425,33 @@ begin if (next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD or next_tx_transaction = READ or next_tx_transaction = READ_ADD) then if not st.read_in_flight or not st.write_in_flight then - st.curr_tx_transaction <= next_tx_transaction; + st.tx_transaction <= next_tx_transaction; st.tx_data_size <= next_tx_data_size; else - st.curr_tx_transaction <= NO_OP; + st.tx_transaction <= NO_OP; st.tx_data_size <= 0; end if; else - st.curr_tx_transaction <= next_tx_transaction; + st.tx_transaction <= next_tx_transaction; st.tx_data_size <= next_tx_data_size; end if; if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE or next_tx_transaction = READ_RESPONSE then - st.curr_tx_addr <= trans_st.write.curr_inst.address; + st.tx_addr <= trans_st.write.inst.address; st.tx_stage <= next_tx_data_size; else - st.curr_tx_addr <= trans_st.read.curr_inst.address; + st.tx_addr <= trans_st.read.inst.address; st.tx_stage <= 0; end if; when TX_HEADER => - if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then - st.last_sent_transaction <= st.curr_tx_transaction; - if not (st.curr_rx_state = RX_HEADER and st.curr_rx_transaction = WRITE_ACK) then + if st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD then + st.last_sent_transaction <= st.tx_transaction; + if not (st.rx_state = RX_HEADER and st.rx_transaction = WRITE_ACK) then st.write_in_flight <= true; end if; - elsif st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD then - st.last_sent_transaction <= st.curr_tx_transaction; - if not (st.curr_rx_state = RX_HEADER and st.curr_rx_transaction = READ_RESPONSE) then + elsif st.tx_transaction = READ or st.tx_transaction = READ_ADD then + st.last_sent_transaction <= st.tx_transaction; + if not (st.rx_state = RX_HEADER and st.rx_transaction = READ_RESPONSE) then st.read_in_flight <= true; end if; end if; @@ -487,9 +465,9 @@ begin end if; when others => end case; - case st.curr_rx_state is + case st.rx_state is when IDLE => - st.curr_rx_transaction <= next_rx_transaction; + st.rx_transaction <= next_rx_transaction; st.rx_data_size <= next_rx_data_size; if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE or next_rx_transaction = READ_RESPONSE then @@ -498,12 +476,12 @@ begin st.rx_stage <= 0; end if; when RX_HEADER => - if st.curr_rx_transaction = WRITE_ACK then - if not (st.curr_tx_state = TX_HEADER and (st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD)) then + if st.rx_transaction = WRITE_ACK then + if not (st.tx_state = TX_HEADER and (st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD)) then st.write_in_flight <= false; end if; if next_rx_transaction /= NO_OP then - st.curr_rx_transaction <= next_rx_transaction; + st.rx_transaction <= next_rx_transaction; st.rx_data_size <= next_rx_data_size; if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE or next_rx_transaction = READ_RESPONSE then @@ -512,8 +490,8 @@ begin st.rx_stage <= 0; end if; end if; - elsif st.curr_rx_transaction = READ_RESPONSE then - if not (st.curr_tx_state = TX_HEADER and (st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD)) then + elsif st.rx_transaction = READ_RESPONSE then + if not (st.tx_state = TX_HEADER and (st.tx_transaction = READ or st.tx_transaction = READ_ADD)) then st.read_in_flight <= false; end if; end if; @@ -522,7 +500,7 @@ begin st.rx_stage <= st.rx_stage - 1; end if; if next_rx_transaction /= NO_OP and st.rx_stage <= 1 then - st.curr_rx_transaction <= next_rx_transaction; + st.rx_transaction <= next_rx_transaction; st.rx_data_size <= next_rx_data_size; if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE or next_rx_transaction = READ_RESPONSE then @@ -541,33 +519,33 @@ begin end if; when RX_AWAIT => st.manager_data <= manager_to_socbridge_driver.data; - if st.curr_tx_transaction = READ_RESPONSE or st.curr_tx_transaction = WRITE_ACK then - if (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then + if st.tx_transaction = READ_RESPONSE or st.tx_transaction = WRITE_ACK then + if (st.rx_transaction = READ or st.rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32)); - elsif (st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD) and (st.rx_stage - 2) mod 4 = 0 then + elsif (st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD) and (st.rx_stage - 2) mod 4 = 0 then st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32)); end if; end if; when ADDR1 => - if st.curr_rx_transaction = READ_ADD then + if st.rx_transaction = READ_ADD then st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data; else st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data; end if; when ADDR2 => - if st.curr_rx_transaction = READ_ADD then + if st.rx_transaction = READ_ADD then st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data; else st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data; end if; when ADDR3 => - if st.curr_rx_transaction = READ_ADD then + if st.rx_transaction = READ_ADD then st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data; else st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data; end if; when ADDR4 => - if st.curr_rx_transaction = READ_ADD then + if st.rx_transaction = READ_ADD then st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data; else st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data; @@ -579,31 +557,22 @@ begin --- TRANSLATOR --- if(rst = '1') then - trans_st.read.curr_state <= IDLE; - trans_st.read.curr_inst.request <= '0'; - trans_st.read.curr_inst.address <= (others => '0'); - trans_st.read.curr_inst.seq_mem_access_count <= 0; - trans_st.read.is_first_word <= '1'; - trans_st.write.curr_state <= IDLE; - trans_st.write.curr_inst.request <= '0'; - trans_st.write.curr_inst.address <= (others => '0'); - trans_st.write.curr_inst.seq_mem_access_count <= 0; - trans_st.write.is_first_word <= '1'; + trans_st <= translator_reset_vec; elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then - trans_st.read.curr_state <= trans_read_next_state; - trans_st.write.curr_state <= trans_write_next_state; - case trans_st.write.curr_state is + trans_st.read.state <= trans_read_next_state; + trans_st.write.state <= trans_write_next_state; + case trans_st.write.state is when IDLE => if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = WRITE - and trans_st.write.curr_inst.request = '0' then - trans_st.write.curr_inst.request <= controller_to_socbridge_driver.request; - trans_st.write.curr_inst.address <= controller_to_socbridge_driver.address; - trans_st.write.curr_inst.seq_mem_access_count <= controller_to_socbridge_driver.seq_mem_access_count; + and trans_st.write.inst.request = '0' then + trans_st.write.inst.request <= controller_to_socbridge_driver.request; + trans_st.write.inst.address <= controller_to_socbridge_driver.address; + trans_st.write.inst.access_count <= controller_to_socbridge_driver.seq_mem_access_count; else end if; trans_st.write.is_first_word <= '1'; when SEND => - if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then + if trans_st.write.inst.access_count mod 256 = 0 then trans_st.write.is_first_word <= '1'; elsif st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD or next_tx_transaction = READ or next_tx_transaction = READ_ADD then @@ -612,17 +581,15 @@ begin trans_st.write.is_first_word <= '0'; end if; when SEND_ACCEPTED => - trans_st.write.curr_inst.seq_mem_access_count <= trans_st.write.curr_inst.seq_mem_access_count - MAX_PKT_SIZE; - trans_st.write.curr_inst.address <= std_logic_vector(unsigned(trans_st.write.curr_inst.address) + MAX_PKT_SIZE); + trans_st.write.inst.access_count <= trans_st.write.inst.access_count - MAX_PKT_SIZE; + trans_st.write.inst.address <= std_logic_vector(unsigned(trans_st.write.inst.address) + MAX_PKT_SIZE); when AWAIT => if ((ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1') - or trans_st.write.curr_inst.seq_mem_access_count <= 0) - and st.curr_tx_state = TX_W_BODY then - trans_st.write.curr_inst.request <= '0'; - trans_st.write.curr_inst.address <= (others => '0'); - trans_st.write.curr_inst.seq_mem_access_count <= 0; + or trans_st.write.inst.access_count <= 0) + and st.tx_state = TX_W_BODY then + trans_st.write.inst <= ctrl_inst_reset_vec; end if; - if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then + if trans_st.write.inst.access_count mod 256 = 0 then trans_st.write.is_first_word <= '1'; elsif st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD or next_tx_transaction = READ or next_tx_transaction = READ_ADD then @@ -632,17 +599,17 @@ begin end if; when others => end case; - case trans_st.read.curr_state is + case trans_st.read.state is when IDLE => if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = READ then - trans_st.read.curr_inst.request <= controller_to_socbridge_driver.request; - trans_st.read.curr_inst.address <= controller_to_socbridge_driver.address; - trans_st.read.curr_inst.seq_mem_access_count <= controller_to_socbridge_driver.seq_mem_access_count; + trans_st.read.inst.request <= controller_to_socbridge_driver.request; + trans_st.read.inst.address <= controller_to_socbridge_driver.address; + trans_st.read.inst.access_count <= controller_to_socbridge_driver.seq_mem_access_count; else end if; trans_st.read.is_first_word <= '1'; when SEND => - if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then + if trans_st.read.inst.access_count mod 256 = 0 then trans_st.read.is_first_word <= '1'; elsif st.last_sent_transaction = WRITE or st.last_sent_transaction = WRITE_ADD or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD then @@ -651,15 +618,13 @@ begin trans_st.read.is_first_word <= '0'; end if; when SEND_ACCEPTED => - trans_st.read.curr_inst.seq_mem_access_count <= trans_st.read.curr_inst.seq_mem_access_count - MAX_PKT_SIZE; - trans_st.read.curr_inst.address <= std_logic_vector(unsigned(trans_st.read.curr_inst.address) + MAX_PKT_SIZE); + trans_st.read.inst.access_count <= trans_st.read.inst.access_count - MAX_PKT_SIZE; + trans_st.read.inst.address <= std_logic_vector(unsigned(trans_st.read.inst.address) + MAX_PKT_SIZE); when AWAIT => - if (ip_to_socbridge_driver.flush = '1' or trans_st.read.curr_inst.seq_mem_access_count <= 0) and st.curr_tx_state = IDLE then - trans_st.read.curr_inst.request <= '0'; - trans_st.read.curr_inst.address <= (others => '0'); - trans_st.read.curr_inst.seq_mem_access_count <= 0; + if (ip_to_socbridge_driver.flush = '1' or trans_st.read.inst.access_count <= 0) and st.tx_state = IDLE then + trans_st.read.inst <= ctrl_inst_reset_vec; end if; - if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then + if trans_st.read.inst.access_count mod 256 = 0 then trans_st.read.is_first_word <= '1'; elsif st.last_sent_transaction = WRITE or st.last_sent_transaction = WRITE_ADD or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD then diff --git a/src/socbridge/socbridge_driver_pkg.vhd b/src/socbridge/socbridge_driver_pkg.vhd index cc22d3b..4154fdf 100644 --- a/src/socbridge/socbridge_driver_pkg.vhd +++ b/src/socbridge/socbridge_driver_pkg.vhd @@ -26,13 +26,12 @@ package socbridge_driver_pkg is type ctrl_inst_t is record request : std_logic; address : std_logic_vector(address_width - 1 downto 0); - seq_mem_access_count : integer; - instruction : instruction_command_t; + access_count : integer; end record ctrl_inst_t; type ctrl_inst_state_rec_t is record - curr_inst : ctrl_inst_t; - curr_state : ctrl_inst_state_t; + inst : ctrl_inst_t; + state : ctrl_inst_state_t; is_first_word : std_logic; end record ctrl_inst_state_rec_t; @@ -48,14 +47,14 @@ package socbridge_driver_pkg is end record ext_protocol_t; type state_rec_t is record - curr_rx_transaction : transaction_t; - curr_tx_transaction : transaction_t; - curr_rx_state: rx_state_t; - curr_tx_state: tx_state_t; + rx_transaction : transaction_t; + tx_transaction : transaction_t; + rx_state: rx_state_t; + tx_state: tx_state_t; ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t; tx_stage, rx_stage : NATURAL; tx_data_size, rx_data_size : integer; - curr_tx_addr : std_logic_vector(31 downto 0); + tx_addr : std_logic_vector(31 downto 0); read_in_flight : boolean; write_in_flight : boolean; last_sent_transaction : transaction_t; @@ -73,6 +72,50 @@ package socbridge_driver_pkg is pure function get_size_bits(size : command_size_t) return std_logic_vector; pure function get_size_bits_sim(size : command_size_t) return std_logic_vector; + constant ctrl_inst_reset_vec : ctrl_inst_t := ( + request => '0', + address => (others => '0'), + access_count => 0 + ); + + constant translator_reset_vec : translator_state_t := ( + read => ( + state => IDLE, + inst => ctrl_inst_reset_vec, + is_first_word => '1' + ), + write => ( + state => IDLE, + inst => ctrl_inst_reset_vec, + is_first_word => '1' + ) + ); + + constant ext_protocol_reset_vec : ext_protocol_t := ( + data => (others => '0'), + clk => '0', + parity => '1' + ); + + constant st_reset_vec : state_rec_t := ( + ext_to_socbridge_driver_reg => ext_protocol_reset_vec, + socbridge_driver_to_ext_reg => ext_protocol_reset_vec, + tx_state => IDLE, + rx_state => IDLE, + tx_stage => 0, + rx_stage => 0, + tx_transaction => NO_OP, + rx_transaction => NO_OP, + tx_data_size => 0, + rx_data_size => 0, + tx_addr => (others => '0'), + manager_addr => (others => '0'), + manager_data => (others => '0'), + read_in_flight => false, + write_in_flight => false, + last_sent_transaction => NO_OP + ); + end package socbridge_driver_pkg; package body socbridge_driver_pkg is