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Successful minimization by keeping putting active reads and writes in state in manager

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Adam 2025-05-21 17:37:56 +02:00
parent 97256e8f47
commit ac2aa8df19
2 changed files with 21 additions and 7 deletions
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25
src/manager/management_unit.vhd
View File

@ -22,6 +22,8 @@ architecture rtl of management_unit is
signal manager_state : manager_state_t;
signal write_address : manager_word_t;
signal read_address : manager_word_t;
signal reading, writing : std_logic;
-- Address indexing whole words, not bytes
signal word_address : natural;
signal cmd : std_logic_vector(1 downto 0);
@ -53,13 +55,13 @@ begin
manager_to_socbridge_driver.ready <= '1';
manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address));
manager_to_socbridge_driver.valid <= '1';
word_address <= local_word_address;
word_address <= local_word_address;
manager_to_controller.cmd <= cmd;
end process comb_proc;
-- tre sorters sätt att avsluta en skrivning:
-- timeout om vi villha det
-- en lastbit genooom axi interface
-- en lastbit genom axi interface
-- vi har fått all data vi begärde.
seq_proc: process(clk)
@ -67,6 +69,8 @@ begin
if rising_edge(clk) then
if rst = '1' then
manager_state <= manager_state_reset_val;
writing <= '0';
reading <= '0';
else
-- Write data from SoCBridge driver to address
if socbridge_driver_to_manager.valid = '1' then
@ -75,23 +79,32 @@ begin
or socbridge_driver_to_manager.address = write_address_index then
-- CLEAR BUFFER TO IP CORE
end if;
-- The middle but of the command part is enough to tell if it is a read or write
if std_logic_vector(to_unsigned(word_address, min_bits_to_determine_address)) = read_address_index(min_bits_to_determine_address - 1 downto 0) then
reading <= '1';
end if;
if std_logic_vector(to_unsigned(word_address, min_bits_to_determine_address)) = write_address_index(min_bits_to_determine_address - 1 downto 0) then
writing <= '1';
end if;
-- Is the controller done executing an instruction
else
if controller_to_manager.done_reading = '1' then
manager_state.memory(0) <= manager_word_reset_val;
reading <= '0';
--manager_state.memory(0) <= manager_word_reset_val;
end if;
if controller_to_manager.done_writing = '1' then
manager_state.memory(1) <= manager_word_reset_val;
writing <= '0';
--manager_state.memory(1) <= manager_word_reset_val;
end if;
end if;
-- Is there a read instruction in memory
if pack(read_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then
if reading = '1' and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then
manager_to_controller.address <= read_address.address & "0000000000";
manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
cmd <= "10";
-- Is there a write instruction in memory
elsif pack(write_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then
elsif writing = '1' and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then
manager_to_controller.address <= write_address.address & "0000000000";
manager_to_controller.driver_id <= "1"; -- Only supports one driver at present
manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;

3
src/manager/management_unit_pkg.vhd
View File

@ -16,7 +16,8 @@ package management_types is
reserved: std_logic_vector(WORD_SIZE - 1 - (22 + 4 + 3) downto 0);
end record manager_word_t;
constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
constant mem_words : natural := 64;
constant mem_words : natural := 2;
constant min_bits_to_determine_address : natural := natural(CEIL(LOG2(real(mem_words))));
constant address_mask : std_logic_vector(WORD_SIZE - 1 downto 0) := std_logic_vector(to_unsigned(mem_words - 1, 32));
type memory_t is array (0 to mem_words - 1) of manager_word_t;