diff --git a/src/ganimede/control_socbridge_tb.vhd b/src/ganimede/control_socbridge_tb.vhd index 10d2985..e961672 100644 --- a/src/ganimede/control_socbridge_tb.vhd +++ b/src/ganimede/control_socbridge_tb.vhd @@ -4,22 +4,83 @@ use IEEE.NUMERIC_STD.all; library work; use work.io_types.all; library socbridge; -use socbridge.tb_pkg.all; +use socbridge.socbridge_driver_tb_pkg.all; +library controller; entity control_socbridge_tb is end entity control_socbridge_tb; architecture tb of control_socbridge_tb is - + + constant cycle : Time := 10 ns; + signal clk, rst : std_logic; + signal cu_to_sb_cmd: command_t; + signal cu_to_sb_address: std_logic_vector(31 downto 0); + signal cmd_size : positive; + signal ext_socbridge_in : ext_socbridge_in_t := ( + payload => (others => '0'), + control => (others => '0') + ); + signal ext_socbridge_out : ext_socbridge_out_t; + signal int_socbridge_in : int_socbridge_in_t; + signal int_socbridge_out : int_socbridge_out_t := ( + payload => (others => '0'), + write_enable_out => '0', + is_full_in => '0' + ); + signal ext_control_input: ext_control_unit_in_t := ( + driver_id => (others => '0'), + address => (others => '0'), + seq_mem_access_count => (others => '0'), + instruction => x"00" + ); + signal int_control_input: int_control_unit_in_t := (active_driver => (others => '0')); + signal ext_control_output: ext_control_unit_out_t; + signal int_control_output: int_control_unit_out_t; begin + + + socbridge_inst: entity socbridge.socbridge_driver + port map( + clk => clk, + rst => rst, + cmd => cu_to_sb_cmd, + address => cu_to_sb_address, + cmd_size => cmd_size, + ext_in => ext_socbridge_in, + ext_out => ext_socbridge_out, + int_in => int_socbridge_in, + int_out => int_socbridge_out + ); + + control_unit_inst: entity controller.control_unit + port map( + clk => clk, + rst => rst, + ext_control_in => ext_control_input, + ext_control_out => ext_control_output, + int_control_in => int_control_input, + int_control_out => int_control_output + ); + clock_proc: process begin for i in 0 to 50 loop wait for cycle / 2; - clock <= not clock; + clk <= not clk; end loop; wait; end process clock_proc; + stimulus_proc: process + begin + + end process stimulus_proc; + + monitor_proc: process + begin + + end process monitor_proc; + end architecture tb; diff --git a/src/ganimede/io_type_pkg.vhd b/src/ganimede/io_type_pkg.vhd index 963e284..32e351d 100644 --- a/src/ganimede/io_type_pkg.vhd +++ b/src/ganimede/io_type_pkg.vhd @@ -21,6 +21,7 @@ package io_types is socbridge: ext_protocol_def_t; end record interface_inst_t; + --- CONTROL UNIT --- type ext_control_unit_in_t is record driver_id: std_logic_vector(number_of_drivers - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0); diff --git a/src/socbridge/socbridge_driver_tb.vhd b/src/socbridge/socbridge_driver_tb.vhd index 104a2ad..057b57a 100644 --- a/src/socbridge/socbridge_driver_tb.vhd +++ b/src/socbridge/socbridge_driver_tb.vhd @@ -5,6 +5,7 @@ library work; use work.socbridge_driver_tb_pkg.all; library ganimede; use ganimede.io_types.all; +library socbridge; entity socbridge_driver_tb is @@ -59,19 +60,19 @@ architecture tb of socbridge_driver_tb is end if; end procedure; - component socbridge_driver is - port( - clk : in std_logic; - rst : in std_logic; - cmd : in command_t; - address : in std_logic_vector(31 downto 0); - cmd_size: in positive; - ext_in : in ext_socbridge_in_t; - ext_out : out ext_socbridge_out_t; - int_in : out int_socbridge_in_t; - int_out : in int_socbridge_out_t - ); - end component socbridge_driver; +-- component socbridge_driver is +-- port( +-- clk : in std_logic; +-- rst : in std_logic; +-- cmd : in command_t; +-- address : in std_logic_vector(31 downto 0); +-- cmd_size: in positive; +-- ext_in : in ext_socbridge_in_t; +-- ext_out : out ext_socbridge_out_t; +-- int_in : out int_socbridge_in_t; +-- int_out : in int_socbridge_out_t +-- ); +-- end component socbridge_driver; begin socbridge_driver_inst: entity work.socbridge_driver