reduced complexity in dummy IP. Now works with buffers with no unnecessary stall

src/dummy_ip/dummy_ip.vhd

@@ -3,44 +3,37 @@ use IEEE.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 
 entity dummy_ip is
-  generic (
-    data_width : natural := 8
-  );
   port (
     clk, rst : in std_logic;
     ready_in, valid_in : in std_logic;
     ready_out, valid_out : out std_logic;
-    data_in : in std_logic_vector(data_width - 1 downto 0);
-    data_out : out std_logic_vector(data_width - 1 downto 0)
+    data_in : in std_logic_vector(8 - 1 downto 0);
+    data_out : out std_logic_vector(8 - 1 downto 0)
   );
 end entity dummy_ip;
 
 architecture rtl of dummy_ip is
-  signal incremented_in : std_logic_vector(data_width - 1 downto 0);
-  signal valid_out_signal : std_logic;
+  signal incremented_in : std_logic_vector(8 - 1 downto 0);
 begin
  
-valid_out <= valid_out_signal;
-data_out  <= incremented_in;  
+comb_proc: process(ready_in, valid_in, data_in, incremented_in)
+begin
+  ready_out <= ready_in;
+end process;
 
-seq_proc: process(clk, data_in, ready_in, valid_in)
+seq_proc: process(clk,rst)
 begin
   if rst = '1' then
-    incremented_in <= (others => '0');
-    valid_out_signal <= '0';
-    ready_out <= '1';
-  else
-    if rising_edge(clk) then
-      if valid_in = '1' then 
-        valid_out_signal <= '1';
-        ready_out <= '0';
-      elsif valid_out_signal = '1' and ready_in = '1' then
-        valid_out_signal <= '0';
-        ready_out <= '1';
-      end if; 
-    elsif falling_edge(clk)then
-      incremented_in <= std_logic_vector(unsigned(data_in) + 1);    
-    end if;
+    valid_out <= '0';
+    data_out <= (others => '0');
+  elsif rising_edge(clk) then
+    if valid_in = '1' and ready_in = '1' then 
+      valid_out <= '1';
+      data_out <= std_logic_vector(unsigned(data_in) + 1);    
+    else
+      valid_out <= '0';
+    end if; 
+  elsif falling_edge(clk) then
   end if;
 end process seq_proc;