Rough outline of new FSMs probably done. All remaining work is hopefully covered by TODOs
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@ -130,11 +130,11 @@ begin
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if PACKET_TYPE = COMMAND then -- TODO Make this a real type and variable
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next_rx_state <= CMD;
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elsif PACKET_TYPE = RESPONSE then
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next_rx_state <= RX_HEADER;
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next_rx_state <= RX_BODY;
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else
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next_rx_state <= IDLE;
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end if;
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when CMD =>
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when CMD =>
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-- TODO This should be changed to not to check 'st.curr_cmd' but rather
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-- the command received which may not be the same variable
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if st.curr_cmd = WRITE_ADD then
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@ -146,64 +146,64 @@ begin
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elsif st.curr_cmd = READ then
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next_rx_state <= GEN_ACCESS;
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end if;
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when RX_HEADER =>
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-- The header only takes one word (cycle) to transmit.
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-- Continue to awaiting response directly afterwards.
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if st.curr_cmd = READ_ADD then
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next_rx_state <= ADDR1;
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else
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next_rx_state <= RX_RESPONSE;
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end if;
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when RX_RESPONSE =>
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-- Wait for read response.
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if curr_response = READ_RESPONSE then
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next_rx_state <= RX_BODY;
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else
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next_rx_state <= RX_RESPONSE;
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end if;
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--when RX_HEADER =>
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---- The header only takes one word (cycle) to transmit.
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---- Continue to awaiting response directly afterwards.
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-- if st.curr_cmd = READ_ADD then
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-- next_rx_state <= ADDR1;
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-- else
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-- next_rx_state <= RX_RESPONSE;
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-- end if;
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--when RX_RESPONSE =>
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---- Wait for read response.
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-- if curr_response = READ_RESPONSE then
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-- next_rx_state <= RX_BODY;
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-- else
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-- next_rx_state <= RX_RESPONSE;
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-- end if;
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when RX_BODY =>
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-- Here we want to stay in RX_BODY for the duration of a packet.
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if st.read_stage = 0 then
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next_rx_state <= IDLE;
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else
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else
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next_rx_state <= RX_BODY;
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end if;
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when ADDR1 =>
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-- Transmits the entire address and returns to the appropriate
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-- Transmits the entire address and returns to the appropriate
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next_rx_state <= ADDR2;
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when ADDR2 =>
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next_rx_state <= ADDR3;
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when ADDR3 =>
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next_rx_state <= ADDR4;
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when ADDR4 =>
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-- TODO Unsure about this case. Should we enter RX_RESPONSE here?
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when ADDR4 =>
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-- TODO this should probably not be dependant on state's instruction
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if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then
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next_rx_state <= PAYLOAD;
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else
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next_rx_state <= RX_RESPONSE;
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else
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next_rx_state <= RX_BODY;
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end if;
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end case;
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--- Next State Assignment Of TX FSM ---
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case st.curr_tx_state is
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when IDLE =>
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-- Do we have a command, if so enter command state.
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if st.curr_cmd = READ_ADD or st.curr_cmd = READ or
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st.curr_cmd = WRITE_ADD or st.curr_cmd = WRITE then
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next_tx_state <= CMD;
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next_tx_state <= TX_HEADER;
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-- Otherwise we are ready to send a response to a read.
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elsif RESPONSE_READY then -- TODO define RESPONSE_READY
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next_tx_state <= RESPONSE;
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else
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next_tx_state <= IDLE;
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end if;
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when CMD =>
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if st.curr_cmd = WRITE_ADD then
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next_tx_state <= TX_HEADER;
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elsif st.curr_cmd = WRITE then
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next_tx_state <= WRITE;
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elsif st.curr_cmd = READ or st.curr_cmd = READ_ADD then
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next_tx_state <= RX_HEADER;
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end if;
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when RESPONSE =>
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-- TODO consider whether this should be moved to TX_BODY
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if MORE_RESPONSE then
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next_tx_state <= RESPONSE;
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else
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next_tx_state <= IDLE;
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end if;
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when TX_HEADER =>
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-- The header only takes one word (cycle) to transmit.
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-- Continue to body or address directly afterwards.
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@ -220,6 +220,7 @@ begin
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next_tx_state <= TX_BODY;
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end if;
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when TX_ACK =>
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-- TODO move this to rx FSM
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-- Wait for write acknowledgement.
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if curr_response = WRITE_ACK then
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next_tx_state <= IDLE;
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@ -237,7 +238,16 @@ begin
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if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then
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next_tx_state <= TX_BODY;
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else
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next_tx_state <= RX_RESPONSE;
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-- If it is a read instruction we wait for response.
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-- TODO separate read from NO_OP and P_ERR
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next_tx_state <= AWAIT;
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end if;
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when AWAIT =>
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-- Wait for RX FSM to get a response
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if st.curr_rx_state = RX_BODY and st.read_stage = 0 then
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next_tx_state <= IDLE;
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else
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next_tx_state <= AWAIT;
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end if;
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end case;
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@ -256,7 +266,7 @@ begin
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else
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end if;
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when TX_HEADER =>
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if st.curr_cmd = WRITE_ADD then
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if st.curr_cmd = WRITE_ADD or st.curr_cmd = READ_ADD then
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socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
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else
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socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
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@ -22,7 +22,7 @@ package socbridge_driver_tb_pkg is
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type tx_state_t is
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(IDLE, ADDR1, ADDR2, ADDR3, ADDR4,
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CMD, RESPONSE, READ, WRITE, PAYLOAD,
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CMD, RESPONSE, READ, WRITE, PAYLOAD, AWAIT,
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TX_HEADER, TX_BODY, TX_ACK);
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--- TRANSLATOR ---
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type translator_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);
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