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inital work on the example socbridge driver

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Erik Örtenberg 2025-02-20 16:23:00 +01:00
parent 34326b4c56
commit bd75d79bb3
1 changed files with 54 additions and 3 deletions
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57
src/socbridge_driver.vhd
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@ -7,7 +7,7 @@ use work.io_types.all;
entity socbridge_driver is entity socbridge_driver is
port( port(
clk : in std_logic; clk : in std_logic;
reset : in std_logic; rst : in std_logic;
ext_in : in ext_socbridge_in_t; ext_in : in ext_socbridge_in_t;
ext_out : out ext_socbridge_out_t; ext_out : out ext_socbridge_out_t;
int_in : out int_socbridge_in_t; int_in : out int_socbridge_in_t;
@ -17,8 +17,59 @@ end entity socbridge_driver;
architecture rtl of socbridge_driver is architecture rtl of socbridge_driver is
signal ext_d_in, ext_d_out,ext_d_in_reg, ext_d_out_reg : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
signal ext_clk_in, ext_clk_out, ext_parity_in, ext_parity_out : std_logic;
type command_t is
(IDLE, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR);
type response_t is
(WRITE_ACK, READ_RESPONSE, UNKNOWN);
type state_t is
(RESET, IDLE, TX_HEADER, TX_BODY, TX_ACK, RX_HEADER, RX_RESPONSE, RX_BODY);
signal curr_state, next_state : state_t;
signal curr_command : command_t;
signal curr_command_bits : std_logic_vector(4 downto 0);
signal curr_respoonse : response_t;
begin begin
ext_out <= (payload => (others => '0'), control => (others => '0')); ext_out.payload <= ext_d_out_reg;
int_in <= (payload => (others => '0'), write_enable_in => '0', is_full_out =>'0'); ext_out.control <= ext_clk_out & ext_parity_out;
ext_d_in <= ext_in.payload;
ext_parity_in <= ext_out.control(0);
ext_clk_in <= ext_out.control(1);
-- Create combinational bindings for command/response types
with curr_command select
curr_command_bits <= "00000" when IDLE,
"10000" when WRITE_ADD,
"10100" when WRITE,
"11000" when READ_ADD,
"11100" when READ,
"01001" when P_ERR,
"11111" when others;
with ext_d_in(7 downto 3) select
curr_respoonse <= WRITE_ACK when "00001" or "00101",
READ_RESPONSE when "01000" or "01100",
UNKNOWN when others;
-- Process updating internal registers based on primary clock
reg_proc: process(ext_clk_in, rst)
begin
if(rst = '1') then
ext_clk_out <= '0';
ext_d_in_reg <= (others => '0');
elsif(rising_edge(ext_clk_in)) then
ext_clk_out <= not ext_clk_out;
ext_d_in_reg <= ext_d_in;
end if;
end process reg_proc;
end architecture rtl; end architecture rtl;