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bidir transfer: now works in socbridge verification tb

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This commit is contained in:
Erik Örtenberg 2025-04-21 17:02:29 +02:00
parent 94fa595d6f
commit c44c153bb3
2 changed files with 20 additions and 16 deletions
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33
src/socbridge/socbridge_driver.vhd
View File

@ -62,7 +62,6 @@ begin
variable local_next_rx_transaction : transaction_t; variable local_next_rx_transaction : transaction_t;
variable local_next_tx_transaction : transaction_t; variable local_next_tx_transaction : transaction_t;
variable local_next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0); variable local_next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
variable curr_tx_addr : std_logic_vector(31 downto 0);
begin begin
-- Helpful Bindings -- -- Helpful Bindings --
next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver.payload(2 downto 0))); next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver.payload(2 downto 0)));
@ -83,12 +82,6 @@ begin
local_next_rx_transaction := WRITE_ACK; local_next_rx_transaction := WRITE_ACK;
elsif curr_response_bits = "01100" or curr_response_bits = "01000" then elsif curr_response_bits = "01100" or curr_response_bits = "01000" then
local_next_rx_transaction := READ_RESPONSE; local_next_rx_transaction := READ_RESPONSE;
end if;
-- determine address to ouput if address is needed
if st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD then
curr_tx_addr := trans_st.read.curr_inst.address;
elsif st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then
curr_tx_addr := trans_st.write.curr_inst.address;
end if; end if;
-- Outputs -- -- Outputs --
socbridge_driver_to_ext.payload <= st.socbridge_driver_to_ext_reg.data; socbridge_driver_to_ext.payload <= st.socbridge_driver_to_ext_reg.data;
@ -251,13 +244,13 @@ begin
end if; end if;
when TX_AWAIT => when TX_AWAIT =>
when ADDR1 => when ADDR1 =>
local_next_data_out := curr_tx_addr(31 downto 24); local_next_data_out := st.curr_tx_addr(31 downto 24);
when ADDR2 => when ADDR2 =>
local_next_data_out := curr_tx_addr(23 downto 16); local_next_data_out := st.curr_tx_addr(23 downto 16);
when ADDR3 => when ADDR3 =>
local_next_data_out := curr_tx_addr(15 downto 8); local_next_data_out := st.curr_tx_addr(15 downto 8);
when ADDR4 => when ADDR4 =>
local_next_data_out := curr_tx_addr(7 downto 0); local_next_data_out := st.curr_tx_addr(7 downto 0);
end case; end case;
--- ### RX_STATE BASED OUTPUT ### --- --- ### RX_STATE BASED OUTPUT ### ---
socbridge_driver_to_manager.valid <= '0'; socbridge_driver_to_manager.valid <= '0';
@ -311,7 +304,7 @@ begin
trans_write_next_state <= AWAIT; trans_write_next_state <= AWAIT;
-- Wait for driver to finish current instruction, then reenter SEND -- Wait for driver to finish current instruction, then reenter SEND
when AWAIT => when AWAIT =>
if trans_st.write.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then if trans_st.write.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then
trans_write_next_state <= IDLE; trans_write_next_state <= IDLE;
elsif st.curr_tx_state = IDLE then elsif st.curr_tx_state = IDLE then
trans_write_next_state <= SEND; trans_write_next_state <= SEND;
@ -341,7 +334,7 @@ begin
trans_read_next_state <= AWAIT; trans_read_next_state <= AWAIT;
-- Wait for driver to finish current instruction, then reenter SEND -- Wait for driver to finish current instruction, then reenter SEND
when AWAIT => when AWAIT =>
if trans_st.read.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then if trans_st.read.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then
trans_read_next_state <= IDLE; trans_read_next_state <= IDLE;
elsif st.curr_tx_state = IDLE then elsif st.curr_tx_state = IDLE then
trans_read_next_state <= SEND; trans_read_next_state <= SEND;
@ -431,8 +424,10 @@ begin
st.tx_data_size <= next_tx_data_size; st.tx_data_size <= next_tx_data_size;
if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE
or next_tx_transaction = READ_RESPONSE then or next_tx_transaction = READ_RESPONSE then
st.curr_tx_addr <= trans_st.write.curr_inst.address;
st.tx_stage <= next_tx_data_size; st.tx_stage <= next_tx_data_size;
else else
st.curr_tx_addr <= trans_st.read.curr_inst.address;
st.tx_stage <= 0; st.tx_stage <= 0;
end if; end if;
when TX_W_BODY => when TX_W_BODY =>
@ -536,6 +531,7 @@ begin
when SEND => when SEND =>
when SEND_ACCEPTED => when SEND_ACCEPTED =>
trans_st.write.curr_inst.seq_mem_access_count <= trans_st.write.curr_inst.seq_mem_access_count - MAX_PKT_SIZE; trans_st.write.curr_inst.seq_mem_access_count <= trans_st.write.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
trans_st.write.curr_inst.address <= std_logic_vector(unsigned(trans_st.write.curr_inst.address) + MAX_PKT_SIZE);
when AWAIT => when AWAIT =>
if trans_st.write.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then if trans_st.write.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
trans_st.write.curr_inst.request <= '0'; trans_st.write.curr_inst.request <= '0';
@ -543,7 +539,13 @@ begin
trans_st.write.curr_inst.seq_mem_access_count <= 0; trans_st.write.curr_inst.seq_mem_access_count <= 0;
trans_st.write.curr_inst.instruction <= NO_OP; trans_st.write.curr_inst.instruction <= NO_OP;
end if; end if;
if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then
trans_st.write.is_first_word <= '1';
elsif trans_st.read.curr_inst.instruction /= NO_OP then
trans_st.write.is_first_word <= '1';
else
trans_st.write.is_first_word <= '0'; trans_st.write.is_first_word <= '0';
end if;
when others => when others =>
end case; end case;
case trans_st.read.curr_state is case trans_st.read.curr_state is
@ -565,8 +567,9 @@ begin
trans_st.read.curr_inst.instruction <= NO_OP; trans_st.read.curr_inst.instruction <= NO_OP;
end if; end if;
if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then
trans_st.read.is_first_word <= '0'; trans_st.read.is_first_word <= '1';
report tost(trans_st.read.curr_inst.address) & " -> " & tost(trans_st.read.curr_inst.address + 256); elsif trans_st.write.curr_inst.instruction /= NO_OP then
trans_st.read.is_first_word <= '1';
else else
trans_st.read.is_first_word <= '0'; trans_st.read.is_first_word <= '0';
end if; end if;

1
src/socbridge/socbridge_driver_pkg.vhd
View File

@ -49,6 +49,7 @@ package socbridge_driver_pkg is
tx_data_size, rx_data_size : integer; tx_data_size, rx_data_size : integer;
curr_write_data : std_logic_vector(31 downto 0); curr_write_data : std_logic_vector(31 downto 0);
curr_read_data : std_logic_vector(31 downto 0); curr_read_data : std_logic_vector(31 downto 0);
curr_tx_addr : std_logic_vector(31 downto 0);
curr_rx_read_addr : std_logic_vector(31 downto 0); curr_rx_read_addr : std_logic_vector(31 downto 0);
curr_rx_write_addr : std_logic_vector(31 downto 0); curr_rx_write_addr : std_logic_vector(31 downto 0);
end record state_rec_t; end record state_rec_t;