diff --git a/src/ganimede.vhd b/src/ganimede.vhd
index 9521259..e95d003 100644
--- a/src/ganimede.vhd
+++ b/src/ganimede.vhd
@@ -14,21 +14,39 @@ entity ganimede is
   );
 end entity ganimede;
 architecture rtl of ganimede is
-  --- SIGNALS INTERFACING THE IP CORE
+  --- SIGNAL DECLERATIONS ---
   signal gan_int_interface_in  : int_interface_in_t;
   signal gan_int_interface_out : int_interface_out_t;
   signal gan_ext_interface_in  : ext_interface_in_t;
   signal gan_ext_interface_out : ext_interface_out_t;
+
+  --signal gan_socbridge_WE_in : std_logic;
+  --signal gan_socbridge_WE_out : std_logic;
+  --signal gan_socbridge_is_full_in : std_logic;
+  --signal gan_socbridge_is_full_out : std_logic;
   
   --- COMPONENT DECLERATIONS ---
+  --component fifo is 
+  --  generic(
+  --    WIDTH : positive;
+  --    DEPTH : positive
+  --  );
+  --  port(
+  --    clk, reset, read_enable, write_enable : in std_logic;
+  --    is_full, is_empty                     : out std_logic;
+  --    data_in      : in std_logic_vector(WIDTH - 1 downto 0);
+  --    data_out     : out std_logic_vector(WIDTH - 1 downto 0)
+  --  );
+  --end component;
+
   component socbridge_driver is
     port(
       clk     : in std_logic;
       reset   : in std_logic;
       ext_in  : in ext_socbridge_in_t;
       ext_out : out ext_socbridge_out_t;
-      int_in  : in int_socbridge_in_t;
-      int_out : out int_socbridge_out_t
+      int_in  : out int_socbridge_in_t;
+      int_out : in int_socbridge_out_t
     );
   end component;
 
@@ -50,12 +68,7 @@ begin
       int_out => gan_int_interface_out.socbridge
   );
 
+  --- LATER WE ADD OPTIMIZATIONS HERE ---
 
 
-
-  --- FIFO - DRIVER  CONNECTION ---
-
-
-  --- FIFO - IP-CORE CONNECTION ---
-
 end architecture rtl;
diff --git a/src/io_type_pkg.vhd b/src/io_type_pkg.vhd
index 48fda5e..3afb8f0 100644
--- a/src/io_type_pkg.vhd
+++ b/src/io_type_pkg.vhd
@@ -33,10 +33,12 @@ package io_types is
 
   type int_socbridge_in_t is record 
       payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
+      write_enable_in, is_full_out : std_logic;
   end record int_socbridge_in_t;
 
   type int_socbridge_out_t is record 
       payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
+      write_enable_out, is_full_in : std_logic;
   end record int_socbridge_out_t;
 
   type ext_interface_in_t is record