From c96300f6fcdae34e13805e39bd4ebc9f09c46ba1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Erik=20=C3=96rtenberg?= Date: Tue, 11 Mar 2025 15:10:21 +0100 Subject: [PATCH] tested and fixed socbridge for multimessage packets --- .../control_socbridge_tb.vhd | 85 +++---------------- src/socbridge/socbridge_driver.vhd | 6 +- 2 files changed, 15 insertions(+), 76 deletions(-) diff --git a/src/control_socbridge_merge/control_socbridge_tb.vhd b/src/control_socbridge_merge/control_socbridge_tb.vhd index af9aa82..e8ad87d 100644 --- a/src/control_socbridge_merge/control_socbridge_tb.vhd +++ b/src/control_socbridge_merge/control_socbridge_tb.vhd @@ -13,7 +13,7 @@ end entity control_socbridge_tb; architecture tb of control_socbridge_tb is constant CLK_PERIOD : Time := 10 ns; - constant SIMULATION_CYCLE_COUNT : integer := 200; + constant SIMULATION_CYCLE_COUNT : integer := 2000; signal clk, rst : std_logic := '0'; signal cu_to_sb_cmd: command_t; signal cu_to_sb_address: std_logic_vector(31 downto 0); @@ -125,7 +125,7 @@ begin ext_control_input.address <= (others => '0'); ext_control_input.cmd <= "00"; ext_control_input.driver_id <= "1"; - ext_control_input.seq_mem_access_count <= 2; + ext_control_input.seq_mem_access_count <= 256; wait for 3 * CLK_PERIOD; report "Reset grace period ended, starting stimulus..."; rst <= '0'; @@ -137,6 +137,7 @@ begin ext_control_input.cmd <= "00"; wait until int_control_input.active_driver(0) = '0'; wait for CLK_PERIOD; + ext_control_input.seq_mem_access_count <= 2; report "Task completed in driver, sending next task..."; ext_control_input.address <= x"FA0FA0FA"; ext_control_input.cmd <= "10"; @@ -169,10 +170,12 @@ begin curr_word <= "00001001"; wait for CLK_PERIOD; curr_word <= "00000000"; - wait for CLK_PERIOD * 20; + wait for CLK_PERIOD * 140; curr_word <= "00101001"; wait for CLK_PERIOD; curr_word <= "00000000"; + wait for CLK_PERIOD * 140; + curr_word <= "00101001"; wait for CLK_PERIOD*20; curr_word <= "01100001"; wait for CLK_PERIOD; @@ -198,76 +201,12 @@ begin input := input + 1 mod 256; wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); - int_socbridge_in.write_enable_out <= '1'; - int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); - input := input + 1 mod 256; - wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; - wait until falling_edge(clk); + for x in 0 to 1000 loop + int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); + input := input + 1 mod 256; + wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; + wait until falling_edge(clk); + end loop; wait; end process internal_stimulus; diff --git a/src/socbridge/socbridge_driver.vhd b/src/socbridge/socbridge_driver.vhd index 3177494..86b4f9d 100644 --- a/src/socbridge/socbridge_driver.vhd +++ b/src/socbridge/socbridge_driver.vhd @@ -300,8 +300,8 @@ begin end if; end if; - if trans_st.curr_inst.seq_mem_access_count > 256 then - next_cmd_size <= 256; + if trans_st.curr_inst.seq_mem_access_count > 128 then + next_cmd_size <= 128; elsif trans_st.curr_inst.seq_mem_access_count > 0 then next_cmd_size <= trans_st.curr_inst.seq_mem_access_count; else @@ -384,7 +384,7 @@ begin trans_st.is_first_word <= '1'; when SEND => when SEND_ACCEPTED => - trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - 256; + trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - 128; when AWAIT => if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_state = IDLE then trans_st.curr_inst.request <= '0';