From cd6ff9a77a43d723550df08a11b4da9234c3fb20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Erik=20=C3=96rtenberg?= Date: Fri, 23 May 2025 15:18:57 +0200 Subject: [PATCH] made buffers work with valid on rising edge --- src/fifo_buffer/fifo_buffer.vhd | 23 +++++--------------- src/fifo_buffer/fifo_deserializer.vhd | 31 ++++++++++++++++----------- src/socbridge/socbridge_driver.vhd | 14 +++++++++--- 3 files changed, 35 insertions(+), 33 deletions(-) diff --git a/src/fifo_buffer/fifo_buffer.vhd b/src/fifo_buffer/fifo_buffer.vhd index a018820..b6bbf69 100644 --- a/src/fifo_buffer/fifo_buffer.vhd +++ b/src/fifo_buffer/fifo_buffer.vhd @@ -35,21 +35,6 @@ architecture rtl of fifo_buffer is signal inverted_in_clock : std_logic; signal customout : std_logic_vector(0 downto 0); -- techmap needs customout and it is does not have a default value for some reason begin - --- DECLARATION OF NX_SYNCRAM ---entity nx_syncram_be is --- generic ( abits : integer := 6; --- dbits : integer := 8 --- ); --- port ( --- clk : in std_ulogic; --- address : in std_logic_vector (abits -1 downto 0); --- datain : in std_logic_vector (dbits -1 downto 0); --- dataout : out std_logic_vector (dbits -1 downto 0); --- enable : in std_logic_vector (dbits/8-1 downto 0); --- write : in std_logic_vector (dbits/8-1 downto 0) --- ); ---end; techmap_ram_inst : entity techmap.syncram_2p generic map(tech => tech, @@ -101,10 +86,12 @@ begin read_pointer <= (others => '0'); write_pointer <= (others => '0'); else - if rising_edge(in_clk) and valid_in = '1' and buffer_full = '0' then - write_pointer <= std_logic_vector(unsigned(write_pointer) + 1); + if rising_edge(in_clk) then + if valid_in = '1' and buffer_full = '0'then + write_pointer <= std_logic_vector(unsigned(write_pointer) + 1); + end if; end if; - if falling_edge(out_clk) then + if rising_edge(out_clk) then if ready_in = '1' and buffer_empty = '0' then read_pointer <= std_logic_vector(unsigned(read_pointer) + 1); valid_out <= '1'; diff --git a/src/fifo_buffer/fifo_deserializer.vhd b/src/fifo_buffer/fifo_deserializer.vhd index 558214b..0b51657 100644 --- a/src/fifo_buffer/fifo_deserializer.vhd +++ b/src/fifo_buffer/fifo_deserializer.vhd @@ -22,26 +22,24 @@ end entity fifo_deserializer; architecture rtl of fifo_deserializer is -constant out_over_in : natural := output_width / input_width; +constant out_over_in : natural := output_width / input_width - 1; type state_t is record count : integer; data : std_logic_vector(output_width - 1 downto 0); + full_word : std_logic; + prev_ready : std_logic; end record state_t; signal st : state_t; begin comb_proc: process(rst,clk,valid_in,ready_in,data_in,st) begin - if st.count = out_over_in then + if st.full_word = '1' and ready_in = '1' then valid_out <= '1'; else valid_out <= '0'; end if; - if not (st.count = out_over_in) and ready_in = '1' then - ready_out <= '1'; - else - ready_out <= '0'; - end if; + ready_out <= ready_in; data_out <= st.data; end process comb_proc; @@ -50,17 +48,26 @@ begin if rst = '1' then st.count <= 0; st.data <= (others => '0'); + st.full_word <= '0'; + st.prev_ready <= '0'; elsif (rising_edge(clk)) then - if st.count = out_over_in then - st.count <= 0; - elsif valid_in = '1' and ready_in = '1' then - st.count <= st.count + 1; + st.prev_ready <= ready_in; + if valid_in = '1' and st.prev_ready = '1' then if endianess = 0 then - st.data((out_over_in - st.count) * input_width - 1 downto (out_over_in - st.count - 1) * input_width) <= data_in; + st.data((out_over_in + 1 - st.count) * input_width - 1 downto (out_over_in - st.count) * input_width) <= data_in; else st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in; end if; end if; + if st.full_word = '1' and ready_in = '1' then + st.full_word <= '0'; + end if; + if st.count = out_over_in and valid_in = '1' then + st.full_word <= '1'; + st.count <= 0; + elsif valid_in = '1' then + st.count <= st.count + 1; + end if; end if; end process seq_proc; diff --git a/src/socbridge/socbridge_driver.vhd b/src/socbridge/socbridge_driver.vhd index f5a3b0e..8d83b67 100644 --- a/src/socbridge/socbridge_driver.vhd +++ b/src/socbridge/socbridge_driver.vhd @@ -13,7 +13,7 @@ use grlib.stdlib.all; entity socbridge_driver is generic( - MAX_PKT_SIZE : integer range 1 to 128 := 128; + MAX_PKT_SIZE : integer range 1 to 128 := 8; BUFFER_SIZE : integer ); port( @@ -246,9 +246,14 @@ begin else local_next_data_out := get_header_bits(st.curr_tx_transaction, st.curr_rx_transaction) & get_size_bits(st.tx_data_size); end if; - when TX_W_BODY => - if st.tx_stage > 0 then + if st.curr_tx_transaction = WRITE then socbridge_driver_to_ip.ready <= '1'; + end if; + when TX_W_BODY => + if st.tx_stage > 1 then + socbridge_driver_to_ip.ready <= '1'; + end if; + if st.tx_stage > 0 then if ip_to_socbridge_driver.fifo.valid = '1' then local_next_data_out := ip_to_socbridge_driver.fifo.data; else @@ -268,6 +273,9 @@ begin local_next_data_out := st.curr_tx_addr(15 downto 8); when ADDR4 => local_next_data_out := st.curr_tx_addr(7 downto 0); + if st.curr_tx_transaction = WRITE_ADD then + socbridge_driver_to_ip.ready <= '1'; + end if; end case; --- ### RX_STATE BASED OUTPUT ### --- socbridge_driver_to_manager.valid <= '0';