kryddan/exjobb-public
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases Wiki Activity

begun work on output logic based on state

Browse Source
This commit is contained in:
Erik Örtenberg 2025-02-25 17:08:20 +01:00
parent 52b3b6a7ca
commit d7638c64cd
2 changed files with 50 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
src/socbridge_driver.vhd
View File

@ -74,7 +74,7 @@ architecture rtl of socbridge_driver is
signal ext_in_rec : ext_protocol_t;
signal ext_out_rec : ext_protocol_t;
signal ext_out_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
signal next_state : state_t;
signal curr_command : command_t;
signal curr_command_bits : std_logic_vector(4 downto 0);
@ -84,13 +84,14 @@ architecture rtl of socbridge_driver is
begin
comb_proc: process(ext_in, int_out, st)
begin
-- Outputs
ext_out <= create_io_type_out_from_ext_protocol(st.ext_out_reg);
int_in.payload <= st.ext_in_reg.data;
-- Helpful Bindings --
ext_in_rec <= create_ext_protocol_from_io_type_in(ext_in);
ext_out <= create_io_type_out_from_ext_protocol(ext_out_rec);
next_parity_out <= calc_parity(int_out.payload);
ext_out.payload <= st.ext_out_reg.data;
ext_out.control <= st.ext_out_reg.clk & st.ext_out_reg.parity;
curr_response_bits <= ext_in_rec.data(7 downto 3);
-- Create combinational bindings for command/response types
next_parity_out <= calc_parity(ext_out_data_cmd);
with curr_command select
curr_command_bits <= "00000" when NO_OP,
"10000" when WRITE_ADD,
@ -131,7 +132,7 @@ begin
-- | | |
-- +-----------+--------------+
--
--- Next State Assignment ---
--- Next State Assignment ---
case st.curr_state is
when IDLE =>
if curr_command = WRITE or curr_command = WRITE_ADD then
@ -174,7 +175,28 @@ begin
-- Right now, we receive only one single word at a time for simplicity
next_state <= IDLE;
end case;
--- Combinatorial output based on current state ---
ext_out_data_cmd <= (others => '0');
int_in.is_full_out <= '1';
int_in.write_enable_in <= '0';
case st.curr_state is
when IDLE =>
when RESET =>
when TX_HEADER =>
curr_command <= WRITE;
ext_out_data_cmd <= curr_command_bits & "001";
when TX_BODY =>
ext_out_data_cmd <= int_out.payload;
int_in.is_full_out <= '0';
when TX_ACK =>
when RX_HEADER =>
curr_command <= READ;
ext_out_data_cmd <= curr_command_bits & "001";
when RX_RESPONSE =>
when RX_BODY =>
end case;
end process comb_proc;
-- Process updating internal registers based on primary clock
seq_proc: process(ext_in_rec.clk, rst)

38
src/socbridge_driver_tb.vhd
View File

@ -33,7 +33,7 @@ architecture tb of socbridge_driver_tb is
);
end component socbridge_driver;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rst : std_logic;
signal ext_in : ext_socbridge_in_t;
signal ext_out : ext_socbridge_out_t;
signal int_in : int_socbridge_in_t;
@ -57,12 +57,11 @@ begin
int_out => int_out
);
ext_in.control(1) <= clk;
real_clk_proc: process
begin
clk <= '0';
for x in 0 to SIMULATION_CYCLE_COUNT*2 loop
clk <= not clk;
ext_in.control(1) <= clk;
wait for CLK_PERIOD / 2;
end loop;
wait;
@ -105,9 +104,11 @@ begin
external_stimulus: process
begin
rst <= '1';
curr_word <= "00000000";
wait for 3 * CLK_PERIOD;
rst <= '0';
curr_word <= "00000000";
wait for CLK_PERIOD / 2;
-- stimulus goes here
wait for CLK_PERIOD*10;
wait;
end process external_stimulus;
@ -115,22 +116,23 @@ begin
internal_stimulus: process
begin
int_out.is_full_in <= '0';
int_out.write_enable_out <= '0';
wait for 3 * CLK_PERIOD;
wait for CLK_PERIOD / 2;
-- stimulus goes here
int_out.write_enable_out <= '1';
int_out.payload <= "00000000";
wait for CLK_PERIOD;
int_out.payload <= "00000001";
wait for CLK_PERIOD;
int_out.payload <= "00000011";
wait for CLK_PERIOD;
int_out.payload <= "00000111";
wait for CLK_PERIOD;
int_out.payload <= "00001111";
wait for CLK_PERIOD;
int_out.payload <= "00011111";
wait for CLK_PERIOD;
int_out.payload <= "00111111";
wait for CLK_PERIOD;
wait until int_in.is_full_out = '0';
int_out.payload <= "00000010";
wait until int_in.is_full_out = '0';
int_out.payload <= "00000100";
wait until int_in.is_full_out = '0';
int_out.payload <= "00001000";
wait until int_in.is_full_out = '0';
int_out.payload <= "00010000";
wait until int_in.is_full_out = '0';
int_out.payload <= "00100000";
wait until int_in.is_full_out = '0';
wait;
end process internal_stimulus;