kryddan/exjobb-public
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precomputed arithemtic

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Adam 2025-05-22 21:44:57 +02:00
parent 9a1eaa0c15
commit e6709770f9
1 changed files with 11 additions and 8 deletions
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17
src/socbridge/socbridge_driver.vhd
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@ -13,7 +13,7 @@ use grlib.stdlib.all;
entity socbridge_driver is entity socbridge_driver is
generic( generic(
MAX_PKT_SIZE : integer range 1 to 128 := 8 MAX_PKT_SIZE : natural range 1 to 128 := 8
); );
port( port(
clk : in std_logic; clk : in std_logic;
@ -31,13 +31,16 @@ entity socbridge_driver is
end entity socbridge_driver; end entity socbridge_driver;
architecture rtl of socbridge_driver is architecture rtl of socbridge_driver is
type slice is array(0 to 3) of natural;
constant next_slice_32_8_upper : slice := (31, 7, 15, 23);
constant next_slice_32_8_lower : slice := (24, 0, 8, 15);
signal next_parity_out : std_logic; signal next_parity_out : std_logic;
signal ext_to_socbridge_driver_rec : ext_protocol_t; signal ext_to_socbridge_driver_rec : ext_protocol_t;
signal next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0); signal next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
signal next_rx_transaction : transaction_t; signal next_rx_transaction : transaction_t;
signal next_tx_transaction : transaction_t; signal next_tx_transaction : transaction_t;
signal next_tx_data_size, next_rx_data_size : integer; signal next_tx_data_size, next_rx_data_size : natural;
signal next_rx_state : rx_state_t; signal next_rx_state : rx_state_t;
signal next_tx_state : tx_state_t; signal next_tx_state : tx_state_t;
signal st : state_rec_t; signal st : state_rec_t;
@ -257,7 +260,7 @@ begin
end if; end if;
when TX_R_BODY => when TX_R_BODY =>
if st.tx_stage > 0 then if st.tx_stage > 0 then
local_next_data_out := st.curr_read_data((((st.tx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.tx_stage - 1) mod 4) + 1) - 1) * 8); local_next_data_out := st.curr_read_data(next_slice_32_8_upper(st.tx_stage mod 4) downto next_slice_32_8_lower(st.tx_stage mod 4));
end if; end if;
when TX_AWAIT => when TX_AWAIT =>
when ADDR1 => when ADDR1 =>
@ -547,7 +550,7 @@ begin
when RX_W_BODY => when RX_W_BODY =>
if st.rx_stage > 0 then if st.rx_stage > 0 then
st.rx_stage <= st.rx_stage - 1; st.rx_stage <= st.rx_stage - 1;
st.curr_write_data((((st.rx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.rx_stage - 1) mod 4) + 1) - 1) * 8) <= st.ext_to_socbridge_driver_reg.data; st.curr_write_data(next_slice_32_8_upper(st.rx_stage mod 4) downto next_slice_32_8_lower(st.rx_stage mod 4)) <= st.ext_to_socbridge_driver_reg.data;
end if; end if;
if (st.rx_stage - 2) mod 4 = 0 and st.rx_data_size - st.rx_stage > 4 then if (st.rx_stage - 2) mod 4 = 0 and st.rx_data_size - st.rx_stage > 4 then
st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32)); st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32));