kryddan/exjobb-public
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases Wiki Activity

Socbridge and controller testbench progress

Browse Source
This commit is contained in:
Adam Magnusson 2025-03-10 15:08:11 +01:00
parent 9de6920910
commit eb574cf2b8
3 changed files with 411 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/controller/control_unit_tb.vhd
View File

@ -22,7 +22,7 @@ architecture tb of control_unit_tb is
signal int_control_input: int_control_unit_in_t := (active_driver => (others => '0'));
signal ext_control_output: ext_control_unit_out_t;
signal int_control_output: int_control_unit_out_t;
signal current_driver : std_logic_vector(2 downto 0) := "000";
signal current_driver : std_logic_vector(0 downto 0) := "0";
shared variable word_counter: natural := 0;
begin
@ -50,14 +50,14 @@ stimulus_proc: process
begin
wait for cycle;
ext_control_input.driver_id <= "010";
int_control_input.active_driver <= "000";
ext_control_input.driver_id <= "1";
int_control_input.active_driver <= "0";
ext_control_input.address <= x"F0F0F0F0";
ext_control_input.seq_mem_access_count <= 3;
ext_control_input.cmd <= "01";
word_counter := 3;
wait for cycle;
current_driver <= "010";
current_driver <= "1";
report "entering loop with word_counter" & integer'image(word_counter);
for_loop: for i in word_counter - 1 downto 0 loop
@ -65,7 +65,7 @@ begin
report "words remaining are " & integer'image(i);
end loop for_loop;
int_control_input.active_driver <= "000";
int_control_input.active_driver <= "0";
report "Stim process done";
wait;
end process stimulus_proc;
@ -76,7 +76,7 @@ begin
wait for cycle;
wait for cycle;
assert int_control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
assert int_control_output.driver_id = "1" report "Incorrect driver_id from control_unit" severity error;
assert int_control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
assert int_control_output.instruction = WRITE report "Incorrect memory op from control_unit" severity error;

413
src/ganimede/control_socbridge_tb.vhd
View File

@ -12,7 +12,8 @@ end entity control_socbridge_tb;
architecture tb of control_socbridge_tb is
constant cycle : Time := 10 ns;
constant CLK_PERIOD : Time := 10 ns;
constant SIMULATION_CYCLE_COUNT : integer := 100;
signal clk, rst : std_logic;
signal cu_to_sb_cmd: command_t;
signal cu_to_sb_address: std_logic_vector(31 downto 0);
@ -32,7 +33,7 @@ architecture tb of control_socbridge_tb is
driver_id => (others => '0'),
address => (others => '0'),
seq_mem_access_count => 0,
cmd => x"00"
cmd => "00"
);
signal int_control_input: int_control_unit_in_t := (active_driver => (others => '0'));
signal ext_control_output: ext_control_unit_out_t;
@ -40,6 +41,43 @@ architecture tb of control_socbridge_tb is
signal driver_to_control: driver_to_control_t;
signal control_to_driver: control_to_driver_t;
signal curr_word : std_logic_vector(ext_socbridge_in.payload'length - 1 downto 0);
signal expected_out : std_logic_vector(ext_socbridge_out.payload'length - 1 downto 0);
procedure fail(error_msg : string) is
begin
wait for CLK_PERIOD;
report "Simulation ending due to: " & error_msg & ". Shutting down..." severity FAILURE;
end procedure;
procedure check_next_state(correct_state: state_t) is
begin
if(not (correct_state = G_next_state)) then
report "Next State is not what was expected, found " & state_t'image(G_next_state)
& " but expected " & state_t'image(correct_state) severity error;
fail("Next State");
end if;
end procedure;
procedure check_data_out(correct_data: std_logic_vector(ext_socbridge_out.payload'length - 1 downto 0)) is
begin
if(not (correct_data = ext_socbridge_out.payload)) then
report "Data out is not what was expected, found " & to_string(ext_socbridge_out.payload)
& " but expected " & to_string(correct_data) severity error;
fail("Data out");
end if;
end procedure;
procedure check_parity(correct_data: std_logic_vector(ext_socbridge_out.payload'length - 1 downto 0)) is
begin
if(not (calc_parity(correct_data) = calc_parity(ext_socbridge_out.payload))) then
report "Parity out is not what was expected, found " & std_logic'image(calc_parity(ext_socbridge_out.payload))
& " but expected " & std_logic'image(calc_parity(correct_data)) severity error;
fail("Parity out");
end if;
end procedure;
begin
socbridge_inst: entity socbridge.socbridge_driver
@ -71,26 +109,383 @@ begin
int_control_input.active_driver(0) <= driver_to_control.is_active;
clock_proc: process
control_clock_proc: process
begin
for i in 0 to 50 loop
wait for cycle / 2;
wait for CLK_PERIOD / 2;
clk <= not clk;
end loop;
wait;
end process clock_proc;
end process control_clock_proc;
stimulus_proc: process
begin
ext_control_input.address <= x"FB0FB0FB";
ext_control_input.cmd <= "01";
ext_control_input.address <= (others => '0');
ext_control_input.cmd <= "00";
ext_control_input.driver_id <= "1";
ext_control_input.seq_mem_access_count <= 5;
ext_control_input.seq_mem_access_count <= 2;
wait for 3 * CLK_PERIOD;
ext_control_input.address <= x"FA0FA0FA";
ext_control_input.cmd <= "01";
wait until int_control_input.active_driver(0) = '1';
ext_control_input.address <= (others => '0');
ext_control_input.cmd <= "00";
wait until int_control_input.active_driver(0) = '0';
wait for CLK_PERIOD;
ext_control_input.address <= x"FA0FA0FA";
ext_control_input.cmd <= "10";
wait until int_control_input.active_driver(0) = '1';
ext_control_input.address <= (others => '0');
ext_control_input.cmd <= "00";
wait until int_control_input.active_driver(0) = '0';
wait for CLK_PERIOD;
wait;
end process stimulus_proc;
monitor_proc: process
begin
wait;
end process monitor_proc;
ext_socbridge_in.control(1) <= clk;
real_clk_proc: process
begin
for x in 0 to SIMULATION_CYCLE_COUNT*2 loop
clk <= not clk;
wait for CLK_PERIOD / 2;
end loop;
wait;
end process real_clk_proc;
external_stimulus_signal: process(curr_word)
begin
ext_socbridge_in.payload <= curr_word;
ext_socbridge_in.control(0) <= calc_parity(curr_word);
end process external_stimulus_signal;
external_stimulus: process
begin
wait for CLK_PERIOD / 1000;
curr_word <= "00000000";
wait for 999 * CLK_PERIOD / 1000;
wait for 2 * CLK_PERIOD;
wait for CLK_PERIOD / 2;
wait for 4* CLK_PERIOD;
curr_word <= "00001001";
wait for CLK_PERIOD;
curr_word <= "00000000";
wait for CLK_PERIOD * 14;
curr_word <= "00101001";
wait for CLK_PERIOD;
curr_word <= "00000000";
wait for CLK_PERIOD*5;
curr_word <= "01100001";
wait for CLK_PERIOD;
curr_word <= "00100000";
wait for CLK_PERIOD;
curr_word <= "00010000";
wait for CLK_PERIOD;
curr_word <= "00000000";
wait;
end process external_stimulus;
internal_stimulus: process
variable input : integer := 0;
begin
int_socbridge_in.is_full_in <= '0';
int_socbridge_in.write_enable_out <= '0';
wait for 3 * CLK_PERIOD;
-- stimulus goes here
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
wait until falling_edge(clk);
wait;
end process internal_stimulus;
end architecture tb;

2
src/ganimede/io_type_pkg.vhd
View File

@ -28,7 +28,7 @@ package io_types is
driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: integer;
cmd: std_logic_vector(inst_word_width - 1 downto 0);
cmd: std_logic_vector(1 downto 0);
end record ext_control_unit_in_t;
type ext_control_unit_out_t is record