From eda5cc3e163812a321c5a1146a1b8eb73340599c Mon Sep 17 00:00:00 2001 From: Adam Date: Tue, 27 May 2025 16:08:54 +0200 Subject: [PATCH] fixed bugs arising from rebase --- src/socbridge/socbridge_driver.vhd | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/socbridge/socbridge_driver.vhd b/src/socbridge/socbridge_driver.vhd index cf3b8e5..b7c4c72 100644 --- a/src/socbridge/socbridge_driver.vhd +++ b/src/socbridge/socbridge_driver.vhd @@ -34,10 +34,9 @@ end entity socbridge_driver; architecture rtl of socbridge_driver is type slice is array(0 to 3) of natural; constant next_slice_32_8_upper : slice := (31, 7, 15, 23); - constant next_slice_32_8_lower : slice := (24, 0, 8, 15); + constant next_slice_32_8_lower : slice := (24, 0, 8, 16); signal next_parity_out : std_logic; - signal ext_to_socbridge_driver_rec : ext_protocol_t; signal next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0); signal next_rx_transaction : transaction_t; signal next_tx_transaction : transaction_t; @@ -53,18 +52,19 @@ architecture rtl of socbridge_driver is --- MANAGEMENT COMMUNICATION --- begin - comb_proc: process(ext_to_socbridge_driver_rec, ip_to_socbridge_driver, + comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver, controller_to_socbridge_driver, st, trans_st) variable curr_response_bits : std_logic_vector(4 downto 0); variable local_next_rx_transaction : transaction_t; variable local_next_tx_transaction : transaction_t; variable local_next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0); + variable ext_to_socbridge_driver_rec : ext_protocol_t; begin -- DEFAULT VALUES -- Helpful Bindings -- - ext_to_socbridge_driver_rec.data <= ext_to_socbridge_driver.payload; - ext_to_socbridge_driver_rec.clk <= ext_to_socbridge_driver.control(1); - ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0); + ext_to_socbridge_driver_rec.data := ext_to_socbridge_driver.payload; + ext_to_socbridge_driver_rec.clk := ext_to_socbridge_driver.control(1); + ext_to_socbridge_driver_rec.parity := ext_to_socbridge_driver.control(0); socbridge_clk <= ext_to_socbridge_driver_rec.clk; socbridge_driver_to_ip.used_slots <= 0; next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver_rec.data(2 downto 0))); @@ -402,12 +402,12 @@ begin next_data_out <= local_next_data_out; end process comb_proc; -- Process updating internal registers based on primary clock - seq_proc: process(ext_to_socbridge_driver_rec.clk, rst, clk) + seq_proc: process(ext_to_socbridge_driver.control(1), rst, clk) begin if(rst = '1') then st <= st_reset_vec; - elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then - st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data; + elsif(rising_edge(ext_to_socbridge_driver.control(1))) then + st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver.payload; -- PARITY CHECK NOT IMPLEMENTED, REMOVING --st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity; st.socbridge_driver_to_ext_reg.data <= next_data_out; @@ -556,7 +556,7 @@ begin if(rst = '1') then trans_st <= translator_reset_vec; - elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then + elsif(rising_edge(ext_to_socbridge_driver.control(1))) then trans_st.read.state <= trans_read_next_state; trans_st.write.state <= trans_write_next_state; case trans_st.write.state is