diff --git a/src/fifo_buffer/fifo_buffer.vhd b/src/fifo_buffer/fifo_buffer.vhd index 32bff25..a968f2b 100644 --- a/src/fifo_buffer/fifo_buffer.vhd +++ b/src/fifo_buffer/fifo_buffer.vhd @@ -10,24 +10,28 @@ use techmap.gencomp.all; entity fifo_buffer is generic ( buffer_size : natural := 64; - tech : integer := 0 + tech : integer := 0; + data_width : natural := 8 ); port ( rst, in_clk, out_clk : in std_logic; - fifo_in : in fifo_interface_t; - fifo_out : out fifo_interface_t + ready_in : in std_logic; + ready_out : out std_logic; + valid_in : in std_logic; + valid_out : out std_logic; + data_in : in std_logic_vector(data_width - 1 downto 0); + data_out : out std_logic_vector(data_width - 1 downto 0) ); end entity fifo_buffer; architecture rtl of fifo_buffer is constant address_bits : natural := integer(ceil(log2(real(buffer_size)))); - signal read_pointer : std_logic_vector(address_bits - 1 downto 0); - signal write_pointer : std_logic_vector(address_bits - 1 downto 0); - signal data_out_signal : std_logic_vector(fifo_width - 1 downto 0); - signal data_in_signal : std_logic_vector(fifo_width - 1 downto 0); + signal read_pointer : std_logic_vector(address_bits - 1 downto 0); + signal write_pointer : std_logic_vector(address_bits - 1 downto 0); signal write_signal : std_logic; signal buffer_full : std_logic; signal buffer_empty : std_logic; + signal inverted_in_clock : std_logic; signal customout : std_logic_vector(0 downto 0); -- techmap needs customout and it is does not have a default value for some reason begin @@ -55,21 +59,21 @@ begin rclk => out_clk, renable => '1', raddress => read_pointer, - dataout => data_out_signal, - wclk => in_clk, + dataout => data_out, + wclk => inverted_in_clock, write => write_signal, waddress => write_pointer, - datain => data_in_signal, + datain => data_in, customclk => in_clk, --NOTE: No clue what this does but it has to be set to something customout => customout ); - - data_in_signal <= fifo_in.data; - fifo_out.data <= data_out_signal; -comb_proc: process(write_pointer, read_pointer) + + inverted_in_clock <= not in_clk; +comb_proc: process(write_pointer, read_pointer, buffer_full, valid_in, rst) variable write_pointer_inc : unsigned(address_bits - 1 downto 0); begin - fifo_out.ready <= not buffer_full; + ready_out <= not buffer_full; + write_signal <= (valid_in and not buffer_full) or rst; write_pointer_inc := unsigned(write_pointer) + 1; customout <= "0"; if write_pointer_inc = unsigned(read_pointer) then @@ -77,7 +81,6 @@ begin else buffer_full <= '0'; end if; - if write_pointer = read_pointer then buffer_empty <= '1'; else @@ -85,29 +88,22 @@ begin end if; end process comb_proc; -seq_proc: process(rst, fifo_in) +seq_proc: process(rst, in_clk, out_clk, buffer_full, valid_in, ready_in, buffer_empty, write_pointer, read_pointer) begin if rst = '1' then - fifo_out.valid <= '0'; read_pointer <= (others => '0'); write_pointer <= (others => '0'); - write_signal <= '0'; - elsif rising_edge(in_clk) then - if fifo_in.valid = '1' and buffer_full = '0' then - write_signal <= '1'; + else + if rising_edge(in_clk) and valid_in = '1' and buffer_full = '0' then write_pointer <= std_logic_vector(unsigned(write_pointer) + 1); - else - write_signal <= '0'; end if; - end if; - if rising_edge(out_clk) and rst = '0' then - if fifo_in.ready = '1' and buffer_empty = '0' then - fifo_out.valid <= '1'; - read_pointer <= std_logic_vector(unsigned(read_pointer) + 1); - write_signal <= '1'; - else - fifo_out.valid <= '0'; - write_signal <= '0'; + if rising_edge(out_clk) then + if ready_in = '1' and buffer_empty = '0' and unsigned(read_pointer) + 1 /= unsigned(write_pointer) then + read_pointer <= std_logic_vector(unsigned(read_pointer) + 1); + valid_out <= '1'; + else + valid_out <= '0'; + end if; end if; end if; end process seq_proc; diff --git a/src/ganimede/ganimede.vhd b/src/ganimede/ganimede.vhd index ab7b64e..816ba67 100644 --- a/src/ganimede/ganimede.vhd +++ b/src/ganimede/ganimede.vhd @@ -77,21 +77,30 @@ begin fifo_buffer_to_ip_inst : entity gan_buffer.fifo_buffer port map( - in_clk => socbridge_clk, --TODO wrong clock + in_clk => socbridge_clk, out_clk => clk, rst => rst, - fifo_in => socbridge_driver_to_buffer, - fifo_out => ganimede_to_ip.socbridge + ready_in => ip_to_ganimede.socbridge.ready, + ready_out => buffer_to_socbridge_driver.ready, + valid_in => socbridge_driver_to_buffer.valid, + valid_out => ganimede_to_ip.socbridge.valid, + data_in => socbridge_driver_to_buffer.data, + data_out => ganimede_to_ip.socbridge.data ); fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer port map( in_clk => clk, - out_clk => clk, + out_clk => socbridge_clk, rst => rst, - fifo_in => ip_to_ganimede.socbridge, - fifo_out => buffer_to_socbridge_driver + ready_in => socbridge_driver_to_buffer.ready, + ready_out => ganimede_to_ip.socbridge.ready, + valid_in => ip_to_ganimede.socbridge.valid, + valid_out => buffer_to_socbridge_driver.valid, + data_in => ip_to_ganimede.socbridge.data, + data_out => buffer_to_socbridge_driver.data ); + --- LATER WE ADD OPTIMIZATIONS HERE --- diff --git a/src/socbridge/socbridge_driver.vhd b/src/socbridge/socbridge_driver.vhd index f831cc1..1bbb5c8 100644 --- a/src/socbridge/socbridge_driver.vhd +++ b/src/socbridge/socbridge_driver.vhd @@ -39,6 +39,7 @@ architecture rtl of socbridge_driver is signal next_rx_state : rx_state_t; signal next_tx_state : tx_state_t; signal st : state_rec_t; + signal valid_out : std_logic; --- TRANSLATOR --- signal trans_st : translator_state_rec_t; signal trans_next_state : translator_state_t; @@ -215,8 +216,6 @@ begin --- Combinatorial output based on current state --- local_next_data_out := (others => '0'); socbridge_driver_to_ip.ready <= '0'; - socbridge_driver_to_ip.valid <= '0'; - socbridge_driver_to_ip.data <= (others => '0'); --- ### TX_STATE BASED OUTPUT ### --- case st.curr_tx_state is when IDLE => @@ -254,8 +253,6 @@ begin when RX_HEADER => when RX_W_BODY => when RX_R_BODY => - socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data; - socbridge_driver_to_ip.valid <= '1'; when RX_AWAIT => if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then socbridge_driver_to_manager.data <= st.curr_write_data; @@ -345,9 +342,10 @@ begin next_tx_transaction <= local_next_tx_transaction; next_rx_transaction <= local_next_rx_transaction; next_data_out <= local_next_data_out; + socbridge_driver_to_ip.valid <= valid_out; end process comb_proc; -- Process updating internal registers based on primary clock - seq_proc: process(ext_to_socbridge_driver_rec.clk, rst, clk) + seq_proc: process(ext_to_socbridge_driver_rec.clk, st.ext_to_socbridge_driver_reg.data, rst, clk) begin if(rst = '1') then st.ext_to_socbridge_driver_reg.data <= (others => '0'); @@ -367,6 +365,8 @@ begin st.curr_rx_write_addr <= (others => '0'); st.curr_write_data <= (others => '0'); st.curr_read_data <= (others => '0'); + socbridge_driver_to_ip.data <= (others => '0'); + valid_out <= '0'; elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data; @@ -410,6 +410,8 @@ begin end if; when RX_HEADER => when RX_R_BODY => + socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data; + valid_out <= '1'; if st.rx_stage > 0 then st.rx_stage <= st.rx_stage - 1; end if;