Renamed some types

src/controller/control_unit.vhd

@@ -8,8 +8,8 @@ entity control_unit is
   
   port (
     clk, rst              : in  std_logic;
-    cpu_to_controller     : in  cpu_to_controller_t;
-    controller_to_cpu     : out controller_to_cpu_t;
+    manager_to_controller     : in  manager_to_controller_t;
+    controller_to_manager     : out controller_to_manager_t;
     drivers_to_controller : in  drivers_to_controller_t;
     controller_to_drivers : out controller_to_drivers_t
   );
@@ -31,7 +31,7 @@ architecture behave of control_unit is
 
 begin
 
-  comb_proc: process(cpu_to_controller, drivers_to_controller, state)
+  comb_proc: process(manager_to_controller, drivers_to_controller, state)
   begin
     ored := '0';
     ready_reduction: for i in 0 to number_of_drivers - 1 loop
@@ -40,7 +40,7 @@ begin
     controller_to_drivers.socbridge.request <= state.curr_driver;
     controller_to_drivers.socbridge.address <= state.address;
     controller_to_drivers.socbridge.seq_mem_access_count <= state.seq_mem_access_count;        
-    controller_to_cpu.ready <= state.ready;
+    controller_to_manager.ready <= state.ready;
     controller_to_drivers.socbridge.instruction <= state.instruction;
   end process comb_proc;
 
@@ -56,10 +56,10 @@ begin
       else
         state.ready <= not ored;
         if ored = '0' then
-          state.address <= cpu_to_controller.address;
-          state.seq_mem_access_count <= cpu_to_controller.seq_mem_access_count;
-          state.curr_driver <= cpu_to_controller.driver_id(0);
-          with cpu_to_controller.cmd select
+          state.address <= manager_to_controller.address;
+          state.seq_mem_access_count <= manager_to_controller.seq_mem_access_count;
+          state.curr_driver <= manager_to_controller.driver_id(0);
+          with manager_to_controller.cmd select
             state.instruction <= WRITE when "01",
                                  READ  when "10",
                                  NO_OP when others;

src/controller/control_unit_tb.vhd

@@ -14,13 +14,13 @@ architecture tb of control_unit_tb is
   constant cycle: Time := 10 ns;
   signal clock: std_logic := '0';
   signal reset: std_logic := '0';
-  signal cpu_to_controller: cpu_to_controller_t := (
+  signal manager_to_controller: manager_to_controller_t := (
                                               (others => '0'),
                                               (others => '0'),
                                               0,
                                               "00");
   signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0'));
-  signal controller_to_cpu: controller_to_cpu_t;
+  signal controller_to_manager: controller_to_manager_t;
   signal controller_to_drivers: controller_to_drivers_t;
   signal current_driver : std_logic_vector(0 downto 0) := "0";
   shared variable word_counter: natural := 0;
@@ -40,8 +40,8 @@ begin
     port map(
     clk             => clock,
     rst             => reset,
-    cpu_to_controller  => cpu_to_controller,
-    controller_to_cpu => controller_to_cpu,
+    manager_to_controller  => manager_to_controller,
+    controller_to_manager => controller_to_manager,
     drivers_to_controller => drivers_to_controller,
     controller_to_drivers => controller_to_drivers
     );
@@ -50,11 +50,11 @@ stimulus_proc: process
 begin
   wait for cycle;
 
-  cpu_to_controller.driver_id <= "1";
+  manager_to_controller.driver_id <= "1";
   drivers_to_controller.socbridge.is_active <= '0';
-  cpu_to_controller.address <= x"F0F0F0F0";
-  cpu_to_controller.seq_mem_access_count <= 3;
-  cpu_to_controller.cmd <= "01";
+  manager_to_controller.address <= x"F0F0F0F0";
+  manager_to_controller.seq_mem_access_count <= 3;
+  manager_to_controller.cmd <= "01";
   word_counter := 3;
   wait for cycle;
   current_driver <= "1";

src/ganimede/ganimede.vhd

@@ -10,8 +10,8 @@ entity ganimede_toplevel is
   port (
     clk               : in  std_logic;
     rst               : in  std_logic;
-    cpu_to_ganimede   : in  cpu_to_controller_t;
-    ganimede_to_cpu   : out controller_to_cpu_t;
+    manager_to_ganimede   : in  manager_to_controller_t;
+    ganimede_to_manager   : out controller_to_manager_t;
     ext_to_ganimede   : in  ext_to_ganimede_t;
     ganimede_to_ext   : out ganimede_to_ext_t;
     ip_to_ganimede    : in  ip_to_ganimede_t;
@@ -54,7 +54,7 @@ begin
   ganimede_to_ext <= drivers_to_ext;
 
   --- DRIVER INSTANTIATION ---
-  socbridge_inst: entity socbridge.socbridge_driver
+  socbridge_inst: entity gan_socbridge.socbridge_driver
     port map(
       clk                            => clk,
       rst                            => rst,
@@ -70,8 +70,8 @@ begin
     port map(
       clk                            => clk,
       rst                            => rst,
-      cpu_to_controller              => cpu_to_ganimede,
-      controller_to_cpu              => ganimede_to_cpu,
+      manager_to_controller              => manager_to_ganimede,
+      controller_to_manager              => ganimede_to_manager,
       drivers_to_controller          => drivers_to_controller,
       controller_to_drivers          => controller_to_drivers
   );

src/ganimede/io_type_pkg.vhd

@@ -23,16 +23,16 @@ package io_types is
   end record interface_inst_t;
 
   --- CONTROL UNIT ---
-  type cpu_to_controller_t is record
+  type manager_to_controller_t is record
     driver_id            : std_logic_vector(number_of_drivers - 1 downto 0);
     address              : std_logic_vector(address_width - 1 downto 0);
     seq_mem_access_count : integer;
-    cmd                  : std_logic_vector(1 downto 0);
-  end record cpu_to_controller_t;
+    cmd                  : std_logic_vector(1 downto 0); --Noop: 00; Write: 01; Read: 10 
+  end record manager_to_controller_t;
 
-  type controller_to_cpu_t is record
+  type controller_to_manager_t is record
     ready : std_logic;
-  end record controller_to_cpu_t;
+  end record controller_to_manager_t;
 
   --- PROTOCOL INFORMATION ---
   constant interface_inst : interface_inst_t := (

src/management_unit/management_unit.vhd

@@ -0,0 +1,77 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use ieee.numeric_std.all;
+library manager;
+use manager.management_types.all;
+library ganimede;
+use ganimede.io_types.all;
+
+entity management_unit is
+  port (
+    clk, rst                    : in std_logic;
+    manager_to_controller       : out manager_to_controller_t;
+    controller_to_manager       : in controller_to_manager_t; 
+    socbridge_driver_to_manager : in socbridge_driver_to_manager_t;
+    manager_to_socbridge_driver : out manager_to_socbridge_driver_t 
+  );
+
+end entity management_unit;
+
+architecture rtl of management_unit is
+  signal manager_state : manager_state_t;
+  signal write_address : manager_word_t;
+  signal read_address  : manager_word_t;
+  signal msg_size      : manager_word_t;
+begin
+  
+read_address  <= manager_state.memory(to_integer(unsigned(read_address_index)));
+write_address <= manager_state.memory(to_integer(unsigned(write_address_index)));
+
+
+comb_proc: process(controller_to_manager, socbridge_driver_to_manager)
+begin
+  -- Read data from manager to SoCBridge driver
+  manager_to_socbridge_driver.data <= manager_state.memory(to_integer(unsigned(socbridge_driver_to_manager.address)));
+  manager_to_socbridge_driver.valid <= '1';
+end process comb_proc;
+
+seq_proc: process(clk)
+begin
+  if rising_edge(clk) then
+    if rst = '1' then
+      manager_state <= manager_state_reset_val;
+    else
+      -- Write data from SoCBridge driver to address
+      if socbridge_driver_to_manager.valid = '1' then
+        manager_state.memory(to_integer(unsigned(socbridge_driver_to_manager.address))) <= socbridge_driver_to_manager.data;
+        if socbridge_driver_to_manager.address = read_address_index
+        or socbridge_driver_to_manager.address = write_address_index then
+          -- CLEAR BUFFER TO IP CORE
+        end if;
+      end if;
+
+      -- Is there a read instruction in memory
+      if read_address /= (others => '0') and controller_to_manager.ready = '1' then
+        manager_to_controller.address <= read_address;
+        manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
+        manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size));
+        manager_to_controller.cmd <= "10";
+      -- Is there a write instruction in memory
+      elsif write_address /= (others => '0') and controller_to_manager.ready = '1' then
+        manager_to_controller.address <= write_address;
+        manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
+        manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size));
+        manager_to_controller.cmd <= "01";
+      else
+      -- No instruction present in memory, all zeroes to control unit
+        manager_to_controller.address <= (others => '0');
+        manager_to_controller.driver_id <= "0"; -- Only supprts one driver at present
+        manager_to_controller.seq_mem_access_count <= 0;
+        manager_to_controller.cmd <= "00";
+      end if;
+    end if;
+  end if;
+end process seq_proc;
+
+end architecture rtl ;

src/management_unit/management_unit_pkg.vhd

@@ -0,0 +1,42 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+library ganimede;
+use ganimede.io_types.all;
+
+package management_types is
+  constant WORD_SIZE : natural := 32;
+  subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0);
+  constant mem_words : natural := 64;
+  type memory_t is array (0 to mem_words - 1) of manager_word_t;
+
+  -- Index in memory array where memory read address is kept.
+  -- Read is active while it is not all zero.
+  constant read_address_index  : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
+  -- Index in memory array where memory write address is kept.
+  -- Write is active while it is not all zero. Mutex with read address
+  constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0') & '1';
+  constant access_size         : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0') & "10";
+
+  -- Status register for debugging
+  type manager_state_t is record
+    memory : memory_t;
+    data_out : manager_word_t;
+  end record manager_state_t;
+
+  -- reset value of status register
+  constant manager_state_reset_val : manager_state_t := ((others => (others => '0')), x"0000");
+
+  type socbridge_driver_to_manager_t is record
+    address : manager_word_t;
+    data : manager_word_t;
+    valid: std_logic;
+  end record socbridge_driver_to_manager_t;
+
+  type manager_to_socbridge_driver_t is record
+    data : manager_word_t;
+    valid : std_logic;
+    ready : std_logic;
+  end record manager_to_socbridge_driver_t;
+
+end package;