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kryddan:ganimede-space-optimized
kryddan:ganimede-single-issue
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kryddan:ganimede-rework
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kryddan:ganimede-single-issue
kryddan:ganimede-multipacket
kryddan:ganimede-rework
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kryddan:ganimede
kryddan:scripts
kryddan:admin
kryddan:main
kryddan:v1.0.0

2 Commits
0747cbfdc9 ... 3cf9a13019

Author SHA1 Message Date
Erik Örtenberg
3cf9a13019 Updated driver with split FSMs, DMA from socbridge works 2025-04-04 16:48:26 +02:00
Erik Örtenberg
842d8b2305 fixed imports for socbridge 2025-04-04 16:47:53 +02:00
5 changed files with 212 additions and 457 deletions
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4
src/ganimede/ganimede_tb.vhd
View File

@ -3,8 +3,8 @@ use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library ganimede;
use ganimede.io_types.all;
library socbridge;
use socbridge.socbridge_driver_tb_pkg.all;
library gan_socbridge;
use gan_socbridge.socbridge_driver_tb_pkg.all;
library controller;
entity ganimede_tb is

8
src/gantry.toml
View File

@ -4,10 +4,6 @@ maintainer = ""
email = ""
version = "0.0.1"
[libraries.socbridge]
vhdl-version = "93c"
path = "socbridge"
[libraries.ganimede]
vhdl-version = "93c"
path = "ganimede"
@ -183,3 +179,7 @@ path = "grlib-com-nx-2024.4-b4295/lib/micron"
[libraries.ahb2ahb]
vhdl-version = "93c"
path = "grlib-com-nx-2024.4-b4295/verification/ahb2ahb"
[libraries.gan_socbridge]
vhdl-version = "93c"
path = "socbridge"

305
src/socbridge/socbridge_driver.vhd
View File

@ -31,15 +31,16 @@ architecture rtl of socbridge_driver is
shared variable next_rx_transaction : transaction_t;
shared variable next_tx_transaction : transaction_t;
signal test : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
signal next_cmd_size : integer;
signal next_tx_data_size, next_rx_data_size : integer;
signal next_rx_state : rx_state_t;
signal next_tx_state : tx_state_t;
signal curr_cmd_bits : std_logic_vector(4 downto 0);
signal curr_response_bits : std_logic_vector(4 downto 0);
signal st : state_rec_t;
--- TRANSLATOR ---
signal trans_st : translator_state_rec_t;
signal trans_next_state : translator_state_t;
--- FSM COMMUNICATION ---
signal tx_sent_response, rx_received_response : std_logic;
begin
--- DEBUG GLOBAL BINDINGS ---
-- synthesis translate_off
@ -47,7 +48,6 @@ begin
G_ext_to_socbridge_driver_rec <= ext_to_socbridge_driver_rec;
G_socbridge_driver_to_ext_data_cmd <=test;
G_curr_command_bits <= curr_cmd_bits;
G_curr_response_bits <= curr_response_bits;
G_st <= st;
G_trans_st <= trans_st;
-- synthesis translate_on
@ -55,30 +55,15 @@ begin
ext_to_socbridge_driver_rec.clk <= ext_to_socbridge_driver.control(1);
ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0);
-- Helpful Bindings --
curr_response_bits <= ext_to_socbridge_driver.payload(7 downto 3); -- CANT USE ext_to_socbridge_driver_REC here for some reason, the assignment becomes stasteful
-- Not sure that the two process method is helping here: if this was a normal
-- signal assignment there would be no confusion.
-- in the case ... <= ext_to_socbridge_driver_rec we get
-- curr_resp | ext_to_socbridge_driver_rec | ext_to_socbridge_driver
-- 00000 | 00000000 | 00001001
-- 00000 | 00001001 | 00001001
-- 00001 | 00001001 | 00001001
-- 00001 | 00001001 | 00001001
--
-- but in the case ... <= ext_to_socbridge_driver we get
-- curr_resp | ext_to_socbridge_driver_rec | ext_to_socbridge_driver
-- 00000 | 00000000 | 00001001
-- 00001 | 00001001 | 00001001
-- 00001 | 00001001 | 00001001
-- 00001 | 00001001 | 00001001
comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver, st, controller_to_socbridge_driver, trans_st)
comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver,
st, controller_to_socbridge_driver, trans_st,
tx_sent_response, rx_received_response)
variable curr_response_bits : std_logic_vector(4 downto 0);
begin
-- Outputs
socbridge_driver_to_ext <= create_io_type_out_from_ext_protocol(st.socbridge_driver_to_ext_reg);
-- Set helper var to current transaction seen at the input.
-- Helpful Bindings --
next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver.payload(2 downto 0)));
curr_response_bits := ext_to_socbridge_driver.payload(7 downto 3);
-- Set helper var to current transaction seen at the input.
next_rx_transaction := NO_OP;
if curr_response_bits = "10000" then
next_rx_transaction := WRITE_ADD;
@ -88,148 +73,140 @@ begin
next_rx_transaction := READ_ADD;
elsif curr_response_bits = "11100" then
next_rx_transaction := READ;
elsif curr_response_bits = "01001" then -- TODO Might have to check bits 2:0
elsif curr_response_bits = "01001" then
next_rx_transaction := P_ERR;
elsif curr_response_bits = "00101" then
elsif curr_response_bits = "00101" or curr_response_bits = "00001" then
next_rx_transaction := WRITE_ACK;
elsif curr_response_bits = "01100" then
elsif curr_response_bits = "01100" or curr_response_bits = "01000" then
next_rx_transaction := READ_RESPONSE;
end if;
-- Outputs --
socbridge_driver_to_ext <= create_io_type_out_from_ext_protocol(st.socbridge_driver_to_ext_reg);
if trans_st.curr_state = IDLE then
socbridge_driver_to_controller.is_active <= '0';
else
socbridge_driver_to_controller.is_active <= '1';
end if;
--- Next State Assignment Of RX FSM ---
case st.curr_rx_state is
when IDLE =>
if st.curr_rx_transaction /= NO_OP then
--next_rx_state <= TX_HEADER;
else
next_rx_state <= IDLE;
end if;
when RX_R_BODY =>
-- Here we want to stay in RX_R_BODY for the duration of a packet.
if st.rx_stage = 0 then
next_rx_state <= IDLE;
else
next_rx_state <= RX_R_BODY;
end if;
when ADDR1 =>
-- Transmits the entire address and returns to the appropriate
next_rx_state <= ADDR2;
when ADDR2 =>
next_rx_state <= ADDR3;
when ADDR3 =>
next_rx_state <= ADDR4;
when ADDR4 =>
if next_rx_transaction = WRITE_ADD then
next_rx_state <= RX_R_BODY;
elsif next_rx_transaction = READ_ADD then
--next_rx_state <= TELL_TX_TO_SEND_A_READ_RESPONSE;
else
next_rx_state <= IDLE; -- Potentially superfluous safety
end if;
end case;
--- Next State Assignments ---
--- ### TX NEXT STATE ASSIGNMENTS ### ---
--- Next State Assignments ---
--- ### TX NEXT STATE ASSIGNMENTS ### ---
case st.curr_tx_state is
when IDLE =>
if next_tx_transaction = READ_ADD or next_tx_transaction = READ or
next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE then
if next_tx_transaction /= NO_OP then
next_tx_state <= TX_HEADER;
-- Otherwise we are ready to send a response to a read.
elsif RESPONSE_READY then -- TODO define RESPONSE_READY
-- IMMEDIATLY GO INTO CORRECT STATE?
--next_tx_state <= RESPONSE;
else
next_tx_state <= IDLE;
end if;
when RESPONSE =>
-- TODO consider whether this should be moved to TX_W_BODY
if st.tx_stage = 0 then
next_tx_state <= IDLE;
else
next_tx_state <= RESPONSE;
end if;
when TX_HEADER =>
-- The header only takes one word (cycle) to transmit.
-- Continue to body or address directly afterwards.
if st.curr_tx_transaction = WRITE_ADD then
-- Commands
if st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = READ_ADD then
next_tx_state <= ADDR1;
else
elsif st.curr_tx_transaction = WRITE then
next_tx_state <= TX_W_BODY;
end if;
when TX_W_BODY =>
-- Here we want to stay in TX_W_BODY for the duration of a packet.
if st.tx_stage = 0 then
elsif st.curr_tx_transaction = READ then
next_tx_state <= TX_AWAIT;
-- Responses
elsif st.curr_tx_transaction = READ_RESPONSE then
next_tx_state <= TX_R_BODY;
else
next_tx_state <= IDLE;
end if;
when TX_R_BODY =>
if st.tx_stage = 0 then
next_tx_state <= IDLE;
else
next_tx_state <= TX_W_BODY;
next_tx_state <= TX_R_BODY;
end if;
when ADDR1 =>
-- Transmits the entire address and returns to the appropriate
next_tx_state <= ADDR2;
when ADDR2 =>
next_tx_state <= ADDR3;
when ADDR3 =>
next_tx_state <= ADDR4;
when ADDR4 =>
if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then
if st.curr_tx_transaction = READ_ADD then
next_tx_state <= TX_AWAIT;
elsif st.curr_tx_transaction = WRITE_ADD then
next_tx_state <= TX_W_BODY;
else
-- If it is a read instruction we wait for response.
-- TODO separate read from NO_OP and P_ERR
next_tx_state <= IDLE;
end if;
when TX_W_BODY =>
if st.tx_stage = 0 then
next_tx_state <= TX_AWAIT;
else
next_tx_state <= TX_W_BODY;
end if;
when TX_AWAIT =>
-- Wait for RX FSM to get a response
if st.curr_rx_transaction = WRITE_ACK or st.curr_rx_transaction = READ_RESPONSE then
if (st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = WRITE)
and st.curr_rx_transaction = WRITE_ACK then
next_tx_state <= IDLE;
elsif (st.curr_tx_transaction = READ_ADD or st.curr_tx_transaction = READ)
and st.curr_rx_transaction = READ_RESPONSE and st.rx_stage = 0 then
next_tx_state <= IDLE;
else
next_tx_state <= TX_AWAIT;
end if;
end case;
--- ### RX NEXT STATE ASSIGNMENTS ### ---
--- Next State Assignment Of RX FSM ---
case st.curr_rx_state is
when IDLE =>
-- Do we have a command, if so enter command state.
if next_rx_transaction = READ_ADD or next_rx_transaction = READ or
next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE then
next_rx_state <= WRITE;
-- Otherwise we are ready to send a response to a read.
elsif RESPONSE_READY then -- TODO define RESPONSE_READY
-- SHOULD WE NOT MOVE TO CORRECT RESPONSE IMMEDIATLY?
next_rx_state <= RESPONSE;
when IDLE =>
if next_rx_transaction /= NO_OP then
next_rx_state <= RX_HEADER;
else
next_rx_state <= IDLE;
end if;
when RX_HEADER =>
-- Commands
if st.curr_rx_transaction = WRITE_ADD or st.curr_rx_transaction = READ_ADD then
next_rx_state <= ADDR1;
elsif st.curr_rx_transaction = WRITE then
next_rx_state <= RX_W_BODY;
elsif st.curr_rx_transaction = READ then
next_rx_state <= RX_AWAIT;
-- Responses
elsif st.curr_rx_transaction = READ_RESPONSE then
next_rx_state <= RX_R_BODY;
else
next_rx_state <= IDLE;
end if;
when RESPONSE =>
-- TODO consider whether this should be moved to rx_W_BODY
when RX_R_BODY =>
if st.rx_stage = 0 then
next_rx_state <= IDLE;
else
next_rx_state <= RESPONSE;
next_rx_state <= RX_R_BODY;
end if;
when RX_W_ACK =>
next_rx_state <= IDLE;
when RX_R_BODY =>
when ADDR1 =>
next_rx_state <= ADDR2;
when ADDR2 =>
next_rx_state <= ADDR3;
when ADDR3 =>
next_rx_state <= ADDR4;
when ADDR4 =>
if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD then
next_rx_state <= RX_R_BODY;
when ADDR4 =>
if st.curr_rx_transaction = READ_ADD then
next_rx_state <= RX_AWAIT;
elsif st.curr_rx_transaction = WRITE_ADD then
next_rx_state <= RX_W_BODY;
else
next_rx_state <= IDLE; -- Potentially superfluous safety
end if;
when RX_W_BODY =>
if st.rx_stage = 0 then
next_rx_state <= RX_AWAIT;
else
next_rx_state <= RX_W_BODY;
end if;
when RX_AWAIT =>
-- Wait for TX FSM to send a response
if (st.curr_rx_transaction = WRITE_ADD or st.curr_rx_transaction = WRITE)
and st.curr_tx_transaction = WRITE_ACK then
next_rx_state <= IDLE;
elsif (st.curr_rx_transaction = READ_ADD or st.curr_rx_transaction = READ)
and st.curr_tx_transaction = READ_RESPONSE then
next_rx_state <= IDLE;
else
-- If it is a read instruction we wait for response.
-- TODO separate read from NO_OP and P_ERR
--next_rx_state <= TX_AWAIT;
next_rx_state <= RX_AWAIT;
end if;
end case;
@ -242,63 +219,48 @@ begin
--- ### TX_STATE BASED OUTPUT ### ---
case st.curr_tx_state is
when IDLE =>
if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then
socbridge_driver_to_ext_data_cmd := get_header_bits(st.curr_tx_transaction) & get_size_bits(st.curr_cmd_size);
elsif st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD then
socbridge_driver_to_ext_data_cmd := get_header_bits(st.curr_tx_transaction) & get_size_bits(st.curr_cmd_size);
else
end if;
when TX_HEADER =>
if st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = READ_ADD then
socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
else
socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
socbridge_driver_to_ip.is_full_out <= '0';
end if;
socbridge_driver_to_ext_data_cmd := get_header_bits(st.curr_tx_transaction, st.curr_rx_transaction) & get_size_bits(st.tx_data_size);
when TX_W_BODY =>
if st.tx_stage > 0 then
socbridge_driver_to_ip.is_full_out <= '0';
socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
else
socbridge_driver_to_ext_data_cmd := (others => '0');
end if;
when TX_HEADER =>
if st.curr_tx_transaction = READ_ADD then
socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
end if;
when TX_AWAIT =>
when ADDR1 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(23 downto 16);
when ADDR2 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(15 downto 8);
when ADDR3 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
when ADDR4 =>
if st.curr_tx_transaction = WRITE_ADD then
when TX_R_BODY =>
if st.tx_stage > 0 then
socbridge_driver_to_ip.is_full_out <= '0';
socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
report integer'image(to_integer(signed(socbridge_driver_to_ext_data_cmd))) & " "& integer'image(to_integer(signed(ip_to_socbridge_driver.payload)));
end if;
when TX_AWAIT =>
when ADDR1 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
when ADDR2 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(23 downto 16);
when ADDR3 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(15 downto 8);
when ADDR4 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
end case;
--- ### RX_STATE BASED OUTPUT ### ---
case st.curr_rx_state is
when IDLE =>
when RX_HEADER =>
when RX_W_BODY =>
-- TODO Add output signals to management unit later
-- TODO REPLACE TWO BELOW
socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
socbridge_driver_to_ip.write_enable_in <= '1';
when RX_R_BODY =>
socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
socbridge_driver_to_ip.write_enable_in <= '1';
when RX_AWAIT =>
when ADDR1 =>
when ADDR2 =>
when ADDR3 =>
when ADDR4 =>
when RX_W_ACK =>
when RX_R_BODY =>
socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
socbridge_driver_to_ip.write_enable_in <= '1';
end case;
next_parity_out <= calc_parity(socbridge_driver_to_ext_data_cmd);
--- DEBUG GLOBAL BINDINGS ---
-- synthesis translate_off
test <= socbridge_driver_to_ext_data_cmd;
-- synthesis translate_on
--- TRANSLATOR ---
--- Next state assignment
case trans_st.curr_state is
when IDLE =>
@ -330,7 +292,7 @@ begin
--- Combinatorial output based on state
next_tx_transaction := NO_OP;
next_cmd_size <= 0;
next_tx_data_size <= 0;
case trans_st.curr_state is
when IDLE =>
when SEND =>
@ -349,11 +311,11 @@ begin
end if;
if trans_st.curr_inst.seq_mem_access_count > MAX_PKT_SIZE then
next_cmd_size <= MAX_PKT_SIZE;
next_tx_data_size <= MAX_PKT_SIZE;
elsif trans_st.curr_inst.seq_mem_access_count > 0 then
next_cmd_size <= trans_st.curr_inst.seq_mem_access_count;
next_tx_data_size <= trans_st.curr_inst.seq_mem_access_count;
else
next_cmd_size <= 0;
next_tx_data_size <= 0;
end if;
when others =>
end case;
@ -372,7 +334,8 @@ begin
st.tx_stage <= 0;
st.rx_stage <= 0;
st.curr_tx_transaction <= NO_OP;
st.curr_cmd_size <= 0;
st.curr_rx_transaction <= NO_OP;
st.tx_data_size <= 0;
st.curr_addr <= (others => '0');
elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
@ -383,34 +346,44 @@ begin
st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
st.socbridge_driver_to_ext_reg.parity <= next_parity_out;
st.curr_tx_state <= next_tx_state;
st.curr_rx_state <= next_rx_state;
case st.curr_tx_state is
when IDLE =>
st.curr_tx_transaction <= next_tx_transaction;
st.curr_cmd_size <= next_cmd_size;
st.tx_data_size <= next_tx_data_size;
st.curr_addr <= trans_st.curr_inst.address;
if next_cmd_size > 0 then
st.tx_stage <= next_cmd_size - 1;
st.rx_stage <= next_cmd_size - 1;
if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE
or next_tx_transaction = READ_RESPONSE then
st.tx_stage <= next_tx_data_size;
else
st.tx_stage <= 0;
end if;
when TX_HEADER =>
when TX_W_BODY =>
if st.tx_stage > 0 then
st.tx_stage <= st.tx_stage - 1;
end if;
when TX_R_BODY =>
if st.tx_stage > 0 then
st.tx_stage <= st.tx_stage - 1;
end if;
when others =>
end case;
case st.curr_rx_state is
when IDLE =>
st.curr_rx_transaction <= next_rx_transaction;
when RX_W_ACK =>
st.curr_tx_transaction <= NO_OP;
st.curr_cmd_size <= 0;
if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
or next_rx_transaction = READ_RESPONSE then
st.rx_stage <= next_rx_data_size;
else
st.rx_stage <= 0;
end if;
when RX_R_BODY =>
if st.rx_stage > 0 then
st.rx_stage <= st.rx_stage - 1;
else
st.curr_tx_transaction <= NO_OP;
st.curr_cmd_size <= 0;
end if;
when RX_W_BODY =>
if st.rx_stage > 0 then
st.rx_stage <= st.rx_stage - 1;
end if;
when others =>
end case;

331
src/socbridge/socbridge_driver_tb.vhd
View File

@ -1,11 +1,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.all;
library work;
use work.socbridge_driver_tb_pkg.all;
library ganimede;
use ganimede.io_types.all;
library socbridge;
library gan_socbridge;
entity socbridge_driver_tb is
@ -14,75 +15,24 @@ end entity socbridge_driver_tb;
architecture tb of socbridge_driver_tb is
signal clk : std_logic := '0';
signal rst : std_logic;
signal cmd : command_t;
signal address : std_logic_vector(31 downto 0);
signal cmd_size : positive;
signal ext_to_socbridge_driver : ext_to_socbridge_driver_t;
signal socbridge_driver_to_ext : socbridge_driver_to_ext_t;
signal ip_to_socbridge_driver : ip_to_socbridge_driver_t;
signal socbridge_driver_to_ip : socbridge_driver_to_ip_t;
signal controller_to_socbridge_driver : controller_to_socbridge_driver_t;
signal socbridge_driver_controller : socbridge_driver_to_controller_t;
signal curr_word : std_logic_vector(ext_to_socbridge_driver.payload'length - 1 downto 0);
signal expected_out : std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0);
signal controller_to_socbridge_driver : controller_to_socbridge_driver_t;
signal socbridge_driver_to_controller : socbridge_driver_to_controller_t;
shared variable done : boolean := FALSE;
constant CLK_PERIOD : TIME := 10 ns;
constant SIMULATION_CYCLE_COUNT : INTEGER := 100;
procedure fail(error_msg : string) is
begin
wait for CLK_PERIOD;
report "Simulation ending due to: " & error_msg & ". Shutting down..." severity FAILURE;
end procedure;
procedure check_next_state(correct_state: state_t) is
begin
if(not (correct_state = G_next_state)) then
report "Next State is not what was expected, found " & state_t'image(G_next_state)
& " but expected " & state_t'image(correct_state) severity error;
fail("Next State");
end if;
end procedure;
procedure check_data_out(correct_data: std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0)) is
begin
if(not (correct_data = socbridge_driver_to_ext.payload)) then
report "Data out is not what was expected, found " & to_string(socbridge_driver_to_ext.payload)
& " but expected " & to_string(correct_data) severity error;
fail("Data out");
end if;
end procedure;
procedure check_parity(correct_data: std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0)) is
begin
if(not (calc_parity(correct_data) = calc_parity(socbridge_driver_to_ext.payload))) then
report "Parity out is not what was expected, found " & std_logic'image(calc_parity(socbridge_driver_to_ext.payload))
& " but expected " & std_logic'image(calc_parity(correct_data)) severity error;
fail("Parity out");
end if;
end procedure;
-- component socbridge_driver is
-- port(
-- clk : in std_logic;
-- rst : in std_logic;
-- cmd : in command_t;
-- address : in std_logic_vector(31 downto 0);
-- cmd_size: in positive;
-- ext_to_socbridge_driver : in ext_to_socbridge_driver_t;
-- socbridge_driver_to_ext : out socbridge_driver_to_ext_t;
-- ip_to_socbridge_driver : out ip_to_socbridge_driver_t;
-- socbridge_driver_to_ip : in socbridge_driver_to_ip_t
-- );
-- end component socbridge_driver;
constant MAX_CYCLE_COUNT : INTEGER := 1000000;
begin
socbridge_driver_inst: entity socbridge.socbridge_driver
socbridge_driver_inst: entity gan_socbridge.socbridge_driver
port map(
clk => clk,
rst => rst,
controller_to_socbridge_driver => controller_to_socbridge_driver,
socbridge_driver_to_controller => socbridge_driver_controller,
socbridge_driver_to_controller => socbridge_driver_to_controller,
ext_to_socbridge_driver => ext_to_socbridge_driver,
socbridge_driver_to_ext => socbridge_driver_to_ext,
ip_to_socbridge_driver => ip_to_socbridge_driver,
@ -91,242 +41,69 @@ begin
ext_to_socbridge_driver.control(1) <= clk;
real_clk_proc: process
variable cycle_count :integer := 0;
begin
for x in 0 to SIMULATION_CYCLE_COUNT*2 loop
while (not done) and (cycle_count < MAX_CYCLE_COUNT) loop
clk <= not clk;
wait for CLK_PERIOD / 2;
end loop;
wait;
end process real_clk_proc;
reset_proc: process
begin
rst <= '1';
wait for CLK_PERIOD * 3;
rst <= '0';
wait;
end process reset_proc;
verify_clk: process
variable last_clk : std_logic;
begin
wait for CLK_PERIOD / 2;
for x in 0 to SIMULATION_CYCLE_COUNT loop
if last_clk = socbridge_driver_to_ext.control(1) then
report "Secondary side clk not correct." severity error;
end if;
last_clk := socbridge_driver_to_ext.control(1);
wait for CLK_PERIOD;
end loop;
wait;
end process verify_clk;
verify_out_signals: process
begin
wait for CLK_PERIOD / 2;
for x in 0 to SIMULATION_CYCLE_COUNT loop
check_data_out(expected_out);
check_parity(expected_out);
wait for CLK_PERIOD;
end loop;
wait;
end process verify_out_signals;
verify_signals : process
begin
expected_out <= "00000000";
wait for 3 * CLK_PERIOD;
wait for CLK_PERIOD / 3;
expected_out <= "00000000";
check_next_state(IDLE);
wait for CLK_PERIOD /4;
check_next_state(TX_HEADER);
wait for CLK_PERIOD * 3 / 4;
expected_out <= get_cmd_bits(WRITE) & get_size_bits_sim(2);
check_next_state(TX_BODY);
wait for CLK_PERIOD;
expected_out <= "00000001";
check_next_state(TX_BODY);
wait for CLK_PERIOD;
expected_out <= "00000010";
check_next_state(TX_ACK);
wait for CLK_PERIOD;
expected_out <= "00000000";
check_next_state(TX_ACK);
wait for CLK_PERIOD;
check_next_state(IDLE);
wait for CLK_PERIOD * 6;
expected_out <= "00000000";
check_next_state(IDLE);
wait for CLK_PERIOD /4;
check_next_state(TX_HEADER);
wait for CLK_PERIOD * 3 / 4;
expected_out <= get_cmd_bits(WRITE_ADD) & get_size_bits(2);
check_next_state(ADDR1);
wait for CLK_PERIOD;
expected_out <= x"FA";
check_next_state(ADDR2);
wait for CLK_PERIOD;
expected_out <= x"A0";
check_next_state(ADDR3);
wait for CLK_PERIOD;
expected_out <= x"0F";
check_next_state(ADDR4);
wait for CLK_PERIOD;
expected_out <= x"FA";
check_next_state(TX_BODY);
wait for CLK_PERIOD;
expected_out <= "00000100";
check_next_state(TX_BODY);
wait for CLK_PERIOD;
expected_out <= "00001000";
check_next_state(TX_ACK);
wait for CLK_PERIOD;
expected_out <= "00000000";
check_next_state(TX_ACK);
wait for CLK_PERIOD;
expected_out <= "00000000";
check_next_state(IDLE);
wait for CLK_PERIOD * 2;
wait for CLK_PERIOD /4;
check_next_state(RX_HEADER);
wait for CLK_PERIOD * 3 / 4;
expected_out <= get_cmd_bits(READ) & get_size_bits(2);
check_next_state(RX_RESPONSE);
wait for CLK_PERIOD;
expected_out <= "00000000";
check_next_state(RX_RESPONSE);
wait for CLK_PERIOD;
check_next_state(RX_BODY);
wait for CLK_PERIOD;
check_next_state(RX_BODY);
wait for CLK_PERIOD;
check_next_state(IDLE);
wait for CLK_PERIOD * 5;
wait for CLK_PERIOD /4;
check_next_state(RX_HEADER);
wait for CLK_PERIOD * 3 / 4;
expected_out <= get_cmd_bits(READ_ADD) & get_size_bits(2);
check_next_state(ADDR1);
wait for CLK_PERIOD;
expected_out <= x"FA";
check_next_state(ADDR2);
wait for CLK_PERIOD;
expected_out <= x"A0";
check_next_state(ADDR3);
wait for CLK_PERIOD;
expected_out <= x"0F";
check_next_state(ADDR4);
wait for CLK_PERIOD;
expected_out <= x"FA";
check_next_state(RX_RESPONSE);
wait for CLK_PERIOD;
expected_out <= "00000000";
check_next_state(RX_RESPONSE);
wait for CLK_PERIOD;
check_next_state(RX_BODY);
wait for CLK_PERIOD;
check_next_state(RX_BODY);
wait for CLK_PERIOD;
check_next_state(IDLE);
wait;
end process verify_signals;
command_stimulus: process
begin
cmd <= NO_OP;
cmd_size <= 2;
wait for 3*CLK_PERIOD;
wait for CLK_PERIOD / 2;
cmd <= WRITE;
wait for CLK_PERIOD;
cmd <= NO_OP;
wait for CLK_PERIOD * 10;
cmd <= WRITE_ADD;
address <= x"FA0FA0FA";
wait for CLK_PERIOD;
cmd <= NO_OP;
address <= (others => '0');
wait for CLK_PERIOD * 10;
cmd <= READ;
wait for CLK_PERIOD;
cmd <= NO_OP;
wait for CLK_PERIOD * 10;
cmd <= READ_ADD;
address <= x"FA0FA0FA";
wait for CLK_PERIOD;
cmd <= NO_OP;
address <= (others => '0');
controller_to_socbridge_driver.instruction <= NO_OP;
controller_to_socbridge_driver.seq_mem_access_count <= 0;
controller_to_socbridge_driver.request <= '0';
controller_to_socbridge_driver.address <= x"00000000";
wait until rst='0';
for i in 100 downto 0 loop
wait until rising_edge(clk);
end loop;
controller_to_socbridge_driver.instruction <= WRITE;
controller_to_socbridge_driver.seq_mem_access_count <= 128;
controller_to_socbridge_driver.address <= x"40000000";
wait until rising_edge(clk);
controller_to_socbridge_driver.request <= '1';
wait until socbridge_driver_to_controller.is_active = '1';
controller_to_socbridge_driver.request <= '0';
wait until socbridge_driver_to_controller.is_active = '0';
for i in 100 downto 0 loop
wait until rising_edge(clk);
end loop;
controller_to_socbridge_driver.instruction <= READ;
controller_to_socbridge_driver.seq_mem_access_count <= 128;
controller_to_socbridge_driver.address <= x"40000000";
wait until rising_edge(clk);
controller_to_socbridge_driver.request <= '1';
wait until socbridge_driver_to_controller.is_active = '1';
controller_to_socbridge_driver.request <= '0';
wait until socbridge_driver_to_controller.is_active = '0';
done := TRUE;
wait;
end process command_stimulus;
external_stimulus_signal: process(curr_word)
begin
ext_to_socbridge_driver.payload <= curr_word;
ext_to_socbridge_driver.control(0) <= calc_parity(curr_word);
end process external_stimulus_signal;
external_stimulus: process
begin
rst <= '0';
wait for CLK_PERIOD / 1000;
rst <= '1';
curr_word <= "00000000";
wait for 999 * CLK_PERIOD / 1000;
wait for 2 * CLK_PERIOD;
rst <= '0';
wait for CLK_PERIOD / 2;
wait for 4* CLK_PERIOD;
curr_word <= "00001001";
wait for CLK_PERIOD;
curr_word <= "00000000";
wait for CLK_PERIOD * 14;
curr_word <= "00101001";
wait for CLK_PERIOD;
curr_word <= "00000000";
wait for CLK_PERIOD*5;
curr_word <= "01000001";
wait for CLK_PERIOD;
curr_word <= "10000000";
wait for CLK_PERIOD;
curr_word <= "01000000";
wait for CLK_PERIOD;
curr_word <= "00000000";
wait for CLK_PERIOD*12;
curr_word <= "01100001";
wait for CLK_PERIOD;
curr_word <= "00100000";
wait for CLK_PERIOD;
curr_word <= "00010000";
wait for CLK_PERIOD;
curr_word <= "00000000";
wait;
end process external_stimulus;
internal_stimulus: process
variable count : integer := 1;
begin
ip_to_socbridge_driver.is_full_in <= '0';
ip_to_socbridge_driver.write_enable_out <= '0';
wait for 3 * CLK_PERIOD;
wait until rst = '0';
-- stimulus goes here
ip_to_socbridge_driver.write_enable_out <= '1';
ip_to_socbridge_driver.payload <= "00000001";
wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
wait until falling_edge(clk);
ip_to_socbridge_driver.payload <= "00000010";
wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
wait until falling_edge(clk);
ip_to_socbridge_driver.payload <= "00000100";
wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
wait until falling_edge(clk);
ip_to_socbridge_driver.payload <= "00001000";
wait until rising_edge(clk) and socbridge_driver_to_ip.is_full_out = '0';
wait until falling_edge(clk);
ip_to_socbridge_driver.payload <= "00010000";
wait until socbridge_driver_to_ip.is_full_out = '0';
wait for CLK_PERIOD/2;
wait until rising_edge(clk);
wait until rising_edge(clk);
ip_to_socbridge_driver.payload <= "00100000";
wait until socbridge_driver_to_ip.is_full_out = '0';
wait for CLK_PERIOD/2;
wait until rising_edge(clk);
wait until rising_edge(clk); --- ??? Why all these rising_edge checks?
while not done loop
wait until (rising_edge(socbridge_driver_to_ext.control(1)) or falling_edge(socbridge_driver_to_ext.control(1))) and socbridge_driver_to_ip.is_full_out = '0';
ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(count, 8));
count := count + 1;
end loop;
wait;
end process internal_stimulus;
end architecture tb ;

21
src/socbridge/socbridge_driver_tb_pkg.vhd
View File

@ -14,12 +14,11 @@ package socbridge_driver_tb_pkg is
type rx_state_t is
(IDLE, ADDR1, ADDR2, ADDR3, ADDR4, RX_AWAIT,
RESPONSE, READ, WRITE, PAYLOAD,
RX_W_ACK, RX_R_BODY, RX_HEADER, RX_W_BODY);
RX_R_BODY, RX_HEADER, RX_W_BODY);
type tx_state_t is
(IDLE, ADDR1, ADDR2, ADDR3, ADDR4, TX_AWAIT,
TX_HEADER, TX_W_BODY, TX_R_BODY, TX_W_ACK);
TX_HEADER, TX_W_BODY, TX_R_BODY);
--- TRANSLATOR ---
type translator_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);
@ -42,7 +41,7 @@ package socbridge_driver_tb_pkg is
curr_tx_state: tx_state_t;
ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t;
tx_stage, rx_stage : NATURAL;
curr_cmd_size: integer;
tx_data_size, rx_data_size : integer;
curr_addr : std_logic_vector(31 downto 0);
end record state_rec_t;
impure function calc_parity(
@ -52,7 +51,7 @@ package socbridge_driver_tb_pkg is
input: ext_protocol_t
) return socbridge_driver_to_ext_t;
function to_string ( a: std_logic_vector) return string;
pure function get_header_bits(command : transaction_t) return std_logic_vector;
pure function get_header_bits(transaction : transaction_t; caused_by: transaction_t) return std_logic_vector;
pure function get_size_bits(size : command_size_t) return std_logic_vector;
pure function get_size_bits_sim(size : command_size_t) return std_logic_vector;
--- DEBUG GLOBAL SIGNALS ---
@ -62,9 +61,7 @@ package socbridge_driver_tb_pkg is
signal G_socbridge_driver_to_ext_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
signal G_next_rx_state : rx_state_t;
signal G_next_tx_state : tx_state_t;
signal G_curr_command : command_t;
signal G_curr_command_bits : std_logic_vector(4 downto 0);
signal G_curr_response : response_t;
signal G_curr_response_bits : std_logic_vector(4 downto 0);
signal G_st : state_rec_t;
signal G_trans_st : translator_state_rec_t;
@ -109,7 +106,7 @@ package body socbridge_driver_tb_pkg is
return val;
end function;
pure function get_header_bits(transaction : transaction_t)
pure function get_header_bits(transaction : transaction_t; caused_by : transaction_t)
return std_logic_vector is
variable val : std_logic_vector(4 downto 0);
begin
@ -124,6 +121,14 @@ package body socbridge_driver_tb_pkg is
val := "11000";
elsif transaction = READ then
val := "11100";
elsif transaction = WRITE_ACK and caused_by = WRITE then
val := "00101";
elsif transaction = WRITE_ACK and caused_by = WRITE_ADD then
val := "00001";
elsif transaction = READ_RESPONSE and caused_by = READ then
val := "01100";
elsif transaction = READ_RESPONSE and caused_by = READ_ADD then
val := "01000";
elsif transaction = P_ERR then
val := "01001";
end if;