socbridge: added support for early termination (flushing) of read/write commands

src/fifo_buffer/fifo_buffer.vhd

@@ -20,7 +20,8 @@ entity fifo_buffer is
     valid_in : in std_logic;
     valid_out : out std_logic;
     data_in : in std_logic_vector(data_width - 1 downto 0);
-    data_out : out std_logic_vector(data_width - 1 downto 0)
+    data_out : out std_logic_vector(data_width - 1 downto 0);
+    used_slots  : out integer range 0 to buffer_size
   );
 end entity fifo_buffer;
 
@@ -73,6 +74,11 @@ begin
 comb_proc: process(write_pointer, read_pointer, buffer_full, valid_in, rst)
   variable write_pointer_inc : unsigned(address_bits - 1 downto 0);
 begin
+  if write_pointer >= read_pointer then
+    used_slots <= to_integer(unsigned(write_pointer) - unsigned(read_pointer));
+  else
+    used_slots <= buffer_size - to_integer(unsigned(read_pointer)) + to_integer(unsigned(write_pointer));
+  end if;
   ready_out <= not buffer_full;
   write_signal <= (valid_in and not buffer_full) or rst;
   write_pointer_inc := unsigned(write_pointer) + 1;

src/ganimede/ganimede.vhd

@@ -29,6 +29,7 @@ architecture rtl of ganimede_toplevel is
   signal manager_to_socbridge_driver : manager_to_socbridge_driver_t;
   signal socbridge_driver_to_buffer : fifo_interface_t;
   signal buffer_to_socbridge_driver : fifo_interface_t;
+  signal ip_to_socbridge_driver : ip_to_socbridge_driver_t;
   signal socbridge_clk : std_logic;
 
   --signal gan_socbridge_WE_in : std_logic;
@@ -37,7 +38,9 @@ architecture rtl of ganimede_toplevel is
   --signal gan_socbridge_is_full_out : std_logic;
   
 begin
-  --- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS ---
+  --- INTERNAL CONNECTIONS ---
+  ip_to_socbridge_driver.fifo <= buffer_to_socbridge_driver;
+  ip_to_socbridge_driver.flush <= ip_to_ganimede.socbridge.flush;
 
   --- DRIVER INSTANTIATION ---
   socbridge_driver_inst: entity gan_socbridge.socbridge_driver
@@ -51,7 +54,7 @@ begin
       socbridge_driver_to_manager    => socbridge_driver_to_manager,
       ext_to_socbridge_driver        => ext_to_ganimede.socbridge,
       socbridge_driver_to_ext        => ganimede_to_ext.socbridge,
-      ip_to_socbridge_driver         => buffer_to_socbridge_driver,
+      ip_to_socbridge_driver         => ip_to_socbridge_driver,
       socbridge_driver_to_ip         => socbridge_driver_to_buffer
     );
 
@@ -78,12 +81,13 @@ begin
   fifo_buffer_to_ip_inst : entity gan_buffer.fifo_buffer
     generic map (
       buffer_size => 1024
+      --tech => 60
     )
     port map(
       in_clk => socbridge_clk,
       out_clk => clk,
       rst => rst,
-      ready_in => ip_to_ganimede.socbridge.ready,
+      ready_in => ip_to_ganimede.socbridge.fifo.ready,
       ready_out => buffer_to_socbridge_driver.ready,
       valid_in => socbridge_driver_to_buffer.valid,
       valid_out => ganimede_to_ip.socbridge.valid,
@@ -94,6 +98,7 @@ begin
   fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer
     generic map (
       buffer_size => 1024
+--      tech => 60
     )
     port map(
       in_clk => clk, 
@@ -101,13 +106,12 @@ begin
       rst => rst,
       ready_in => socbridge_driver_to_buffer.ready,
       ready_out => ganimede_to_ip.socbridge.ready,
-      valid_in => ip_to_ganimede.socbridge.valid,
+      valid_in => ip_to_ganimede.socbridge.fifo.valid,
       valid_out => buffer_to_socbridge_driver.valid,
-      data_in => ip_to_ganimede.socbridge.data,
-      data_out => buffer_to_socbridge_driver.data
+      data_in => ip_to_ganimede.socbridge.fifo.data,
+      data_out => buffer_to_socbridge_driver.data,
+      used_slots => buffer_to_socbridge_driver.used_slots
     );
     
-  --- LATER WE ADD OPTIMIZATIONS HERE ---
-
 
 end architecture rtl;

src/ganimede/io_type_pkg.vhd

@@ -16,6 +16,7 @@ package io_types is
   type fifo_interface_t is record
     ready, valid : std_logic;
     data : std_logic_vector(fifo_width - 1 downto 0);
+    used_slots : integer;
   end record fifo_interface_t;
 
   type ext_protocol_def_t is record
@@ -70,7 +71,10 @@ package io_types is
 
   subtype socbridge_driver_to_ip_t is fifo_interface_t;
 
-  subtype ip_to_socbridge_driver_t is fifo_interface_t;
+  type ip_to_socbridge_driver_t is record
+    fifo: fifo_interface_t;
+    flush: std_logic;
+  end record ip_to_socbridge_driver_t;
 
   type controller_to_drivers_t is record
     socbridge : controller_to_socbridge_driver_t;

src/manager/management_unit.vhd

@@ -76,10 +76,13 @@ begin
           -- CLEAR BUFFER TO IP CORE
         end if;
       -- Is the controller done executing an instruction
-      elsif controller_to_manager.done_reading = '1' then
-        manager_state.memory(0) <= manager_word_reset_val;
-      elsif controller_to_manager.done_writing = '1' then
-        manager_state.memory(1) <= manager_word_reset_val;
+      else
+        if controller_to_manager.done_reading = '1' then
+          manager_state.memory(0) <= manager_word_reset_val;
+        end if;
+        if controller_to_manager.done_writing = '1' then
+          manager_state.memory(1) <= manager_word_reset_val;
+        end if;
       end if;
       -- Is there a read instruction in memory
       if pack(read_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then

src/socbridge/socbridge_driver.vhd

@@ -238,8 +238,8 @@ begin
       when TX_W_BODY =>
         if st.tx_stage > 0 then
           socbridge_driver_to_ip.ready <= '1';
-          if ip_to_socbridge_driver.valid = '1' then
-            local_next_data_out := ip_to_socbridge_driver.data;
+          if ip_to_socbridge_driver.fifo.valid = '1' then
+            local_next_data_out := ip_to_socbridge_driver.fifo.data;
           else
             local_next_data_out := (others => '0');
           end if;
@@ -293,7 +293,8 @@ begin
         if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD
         or st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
           trans_write_next_state <= IDLE;
-        elsif trans_st.write.curr_inst.request = '1' then
+        elsif trans_st.write.curr_inst.request = '1' and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE 
+          or ip_to_socbridge_driver.flush = '1') then
           trans_write_next_state <= SEND;
         else 
           trans_write_next_state <= IDLE;
@@ -312,7 +313,11 @@ begin
       when AWAIT =>
         if trans_st.write.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then
           trans_write_next_state <= IDLE;
-        elsif st.curr_tx_state = IDLE then
+        elsif ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1'
+              and st.curr_tx_state = IDLE then
+          trans_write_next_state <= IDLE;
+        elsif st.curr_tx_state = IDLE and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE
+          or ip_to_socbridge_driver.flush = '1') then
           trans_write_next_state <= SEND;
         else 
           trans_write_next_state <= AWAIT;
@@ -345,6 +350,8 @@ begin
       when AWAIT =>
         if trans_st.read.curr_inst.seq_mem_access_count <= MAX_PKT_SIZE and st.curr_tx_state = IDLE then
           trans_read_next_state <= IDLE;
+        elsif ip_to_socbridge_driver.flush = '1'and st.curr_tx_state = IDLE then
+          trans_read_next_state <= IDLE;
         elsif st.curr_tx_state = IDLE then
           trans_read_next_state <= SEND;
         else 
@@ -543,7 +550,9 @@ begin
           trans_st.write.curr_inst.seq_mem_access_count <= trans_st.write.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
           trans_st.write.curr_inst.address <= std_logic_vector(unsigned(trans_st.write.curr_inst.address) + MAX_PKT_SIZE);
         when AWAIT =>
-          if trans_st.write.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
+          if  ((ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1') 
+              or trans_st.write.curr_inst.seq_mem_access_count <= 0) 
+              and st.curr_tx_state = TX_W_BODY then
             trans_st.write.curr_inst.request <= '0';
             trans_st.write.curr_inst.address <= (others => '0');
             trans_st.write.curr_inst.seq_mem_access_count <= 0;
@@ -570,7 +579,7 @@ begin
           trans_st.read.curr_inst.seq_mem_access_count <= trans_st.read.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
           trans_st.read.curr_inst.address <= std_logic_vector(unsigned(trans_st.read.curr_inst.address) + MAX_PKT_SIZE);
         when AWAIT =>
-          if trans_st.read.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
+          if (ip_to_socbridge_driver.flush = '1' or trans_st.read.curr_inst.seq_mem_access_count <= 0) and st.curr_tx_state = IDLE then
             trans_st.read.curr_inst.request <= '0';
             trans_st.read.curr_inst.address <= (others => '0');
             trans_st.read.curr_inst.seq_mem_access_count <= 0;