added initial test of types needed for ganimede IO

Reviewed-on: #3
Reviewed-by: Adam <admag2001@gmail.com>

scripts/elab.py

@@ -22,7 +22,7 @@ def runDesign(topDef: str, arch: str, lib: str, std: str):
     wavePath = os.path.join(os.getcwd(), "wave")
     command = [ ## may add -v for verbose
         "ghdl", "-r", f"{topDef}", f"{arch}", 
-        f"--wave={os.path.join(libPath, topDef)}-{arch}.ghw" ##, "--read-wave-opt=<See"
+        f"--wave=../wave/{topDef}-{arch}.ghw" ##, "--read-wave-opt=<See"
             ]
     subprocess.run(command, cwd=libPath)
     command = [

scripts/gantry.py

@@ -1,5 +1,5 @@
 import typer
-import elab
+import elab as elaborate
 import build_env
 from typing_extensions import Annotated
 
@@ -28,7 +28,7 @@ def elab(
         std: Annotated[str, typer.Option(help="Which VHDL standard to use. 87, 93, 93c, 00, 02 or 08", autocompletion=complete_vhdl_ver)] = "93c"
         ):
     print(f"Elaborating {topdef} with arch {arch} in library {library}. VHDL {std}")
-    return elab.elabDesign(topdef, arch, library, std)
+    return elaborate.elabDesign(topdef, arch, library, std)
 
 @software.command(help="Simulates elaborated design in GHDL and views waves in gtkwave. Automatically runs `gantry elab` on the same top def and arch.")
 def run(
@@ -38,7 +38,7 @@ def run(
         std: Annotated[str, typer.Option(help="Which VHDL standard to use. 87, 93, 93c, 00, 02 or 08", autocompletion=complete_vhdl_ver)] = "93c"
         ):
     print(f"Running (and synthesizing if needed) {topdef} with arch {arch} in library {library}. VHDL {std}")
-    return elab.runDesign(topdef, arch, library, std)
+    return elaborate.runDesign(topdef, arch, library, std)
 
 @hardware.command()
 def build():

src/io_type_pkg.vhd

@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+package io_types is
+
+  type interface_def_t is record
+    name: string (1 to 20);
+    payload_width, control_width: natural;
+  end record interface_def_t;
+
+  type interface_arr_t is array (natural range <>) of interface_def_t;
+    
+  constant interface_arr : interface_arr_t := (
+    0 => ("SoCBridge x         ", 8, 2),
+    1 => ("SoCBridge  x        ", 8, 2),
+    2 => ("SoCBridge   x       ", 8, 2),
+    3 => ("SoCBridge    x      ", 8, 2),
+    4 => ("SoCBridge     x     ", 8, 2),
+    5 => ("SoCBridge      x    ", 8, 2)
+  );
+  
+end package io_types;

src/test.vhd

@@ -0,0 +1,25 @@
+library IEEE;
+library work;
+use work.io_types.all;
+
+entity test is
+  port (
+    t : in interface_arr_t(0 to interface_arr'length - 1)
+  );
+end entity test;
+
+architecture rtl of test is
+  
+begin
+  
+  proc_name: process
+  begin
+    
+    for x in 0 to (interface_arr'length - 1) loop
+      report interface_arr(x).name ;
+    end loop;
+  wait;
+  end process proc_name;
+  
+  
+end architecture rtl;