begun work on output logic based on state

src/socbridge_driver.vhd

@@ -16,6 +16,26 @@ entity socbridge_driver is
 end entity socbridge_driver;
 
 architecture rtl of socbridge_driver is
+  type command_t is 
+    (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR);
+
+  type response_t is 
+    (NO_OP, WRITE_ACK, READ_RESPONSE);
+
+  type state_t is
+    (RESET, IDLE, TX_HEADER, TX_BODY, TX_ACK, RX_HEADER, RX_RESPONSE, RX_BODY);
+
+  type ext_protocol_t is record
+    data   : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+    clk    : std_logic;
+    parity : std_logic;
+  end record ext_protocol_t;
+
+  type state_rec_t is record
+    curr_state: state_t;
+    ext_in_reg, ext_out_reg : ext_protocol_t; 
+  end record state_rec_t;
+
   pure function calc_parity(
     d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)
   ) return std_logic is
@@ -28,35 +48,50 @@ architecture rtl of socbridge_driver is
     return not parity;
   end function;
   
-  signal ext_d_in, ext_d_out,ext_d_in_reg, ext_d_out_reg : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
-  signal ext_clk_in, ext_clk_out, ext_parity_in, ext_parity_out, ext_next_parity_out : std_logic;
+  pure function create_ext_protocol_from_io_type_in(
+    input : ext_socbridge_in_t
+  ) return ext_protocol_t is
+  variable val : ext_protocol_t;
+  begin
+    val.data := input.payload;
+    val.clk := input.control(1);
+    val.parity := input.control(0);
+    return val;
+  end function;
+  pure function create_io_type_out_from_ext_protocol(
+    input : ext_protocol_t
+  ) return ext_socbridge_out_t is
+  variable val : ext_socbridge_out_t;
+  begin
+    val.payload:= input.data;
+    val.control(1) := input.clk;
+    val.control(0) := input.parity;
+    return val;
+  end function;
+  
+  signal next_parity_out : std_logic;
 
 
-  type command_t is 
-    (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR);
 
-  type response_t is 
-    (NO_OP, WRITE_ACK, READ_RESPONSE);
-
-  type state_t is
-    (RESET, IDLE, TX_HEADER, TX_BODY, TX_ACK, RX_HEADER, RX_RESPONSE, RX_BODY);
-
-  signal curr_state, next_state : state_t;
+  signal ext_in_rec : ext_protocol_t;
+  signal ext_out_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  signal next_state : state_t;
   signal curr_command : command_t;
   signal curr_command_bits : std_logic_vector(4 downto 0);
   signal curr_respoonse : response_t;
   signal curr_response_bits : std_logic_vector(4 downto 0);
+  signal st : state_rec_t;
 begin
-  comb_proc: process(ext_in, int_out, ext_d_out_reg, ext_clk_out, ext_parity_out, curr_state)
+  comb_proc: process(ext_in, int_out, st)
   begin
-    ext_next_parity_out <= calc_parity(int_out.payload);
-    ext_out.payload <= ext_d_out_reg;
-    ext_out.control <= ext_clk_out & ext_parity_out;
-    ext_d_in <= ext_in.payload;
-    ext_parity_in <= ext_in.control(0);
-    ext_clk_in <= ext_in.control(1);
-    curr_response_bits <= ext_d_in(7 downto 3);
-    -- Create combinational bindings for command/response types
+    -- Outputs 
+    ext_out <= create_io_type_out_from_ext_protocol(st.ext_out_reg);
+    int_in.payload <= st.ext_in_reg.data;
+
+    -- Helpful Bindings --
+    ext_in_rec <= create_ext_protocol_from_io_type_in(ext_in);
+    curr_response_bits <= ext_in_rec.data(7 downto 3);
+    next_parity_out <= calc_parity(ext_out_data_cmd);
     with curr_command select
       curr_command_bits <= "00000" when NO_OP,
                            "10000" when WRITE_ADD,
@@ -72,7 +107,33 @@ begin
                         READ_RESPONSE when "01100",
                         NO_OP when others;
 
-    case curr_state is
+    --- State Transition Diagram ---
+--                                                            
+--            +-----+                                         
+--           \|/    |                                         
+--          RESET --+                                         
+--            |                                               
+--            |                                               
+--          IDLE<-------------------+                 
+--          /  \                    |                            
+--         /     \                  |                            
+--        /       \                 |                            
+--      \|/       \|/               |                         
+--  TX_HEADER   RX_HEADER           |                        
+--       |           |              |                           
+--       |           |     ----+    |                           
+--      \|/         \|/   \|/  |    |                           
+--   TX_BODY     RX_RESPONSE---+    |                           
+--       |           |              |                           
+--       |  +--+     |              |                           
+--      \|/\|/ |    \|/             |                           
+--     TX_ACK--+ RX_BODY            |                           
+--       |           |              |                           
+--       |           |              |                           
+--       +-----------+--------------+                 
+--                                                            
+  --- Next State Assignment --- 
+    case st.curr_state is
       when IDLE => 
         if curr_command = WRITE or curr_command = WRITE_ADD then
           next_state <= TX_HEADER;
@@ -82,31 +143,79 @@ begin
           next_state <= IDLE;
         end if;
       when RESET =>
+        next_state <= IDLE;
       when TX_HEADER =>
+      -- The header only takes one word (cycle) to transmit.
+      -- Continue to body directly afterwards. 
+        next_state <= TX_BODY;
       when TX_BODY =>
+      -- Here we want to stay in TX_BODY for the duration of a packet.
+      -- Right now, we transfer one single word at a time for simplicity
+        next_state <= TX_ACK;
+      when TX_ACK =>
+      -- Wait for write acknowledgement. 
+        if curr_respoonse = WRITE_ACK then
+          next_state <= IDLE;
+        else 
+          next_state <= TX_ACK;
+        end if;
+      when RX_HEADER =>
+      -- The header only takes one word (cycle) to transmit.
+      -- Continue to awaiting response directly afterwards.
+        next_state <= RX_RESPONSE;
+      when RX_RESPONSE =>
+      -- Wait for read response. 
+        if curr_respoonse = READ_RESPONSE then
+          next_state <= RX_BODY;
+        else 
+          next_state <= RX_RESPONSE;
+        end if;
+      when RX_BODY =>
+      -- Here we want to stay in RX_BODY for the duration of a packet.
+      -- Right now, we receive only one single word at a time for simplicity
+        next_state <= IDLE;
+    end case;
+    
+  --- Combinatorial output based on current state ---
+    ext_out_data_cmd <= (others => '0');
+    int_in.is_full_out <= '1';
+    int_in.write_enable_in <= '0';
+    case st.curr_state is
+      when IDLE => 
+      when RESET =>
+      when TX_HEADER =>
+        curr_command <= WRITE;
+        ext_out_data_cmd <= curr_command_bits & "001";
+      when TX_BODY =>
+        ext_out_data_cmd <= int_out.payload;
+        int_in.is_full_out <= '0';
       when TX_ACK =>
       when RX_HEADER =>
+        curr_command <= READ;
+        ext_out_data_cmd <= curr_command_bits & "001";
       when RX_RESPONSE =>
       when RX_BODY =>
     end case;
-  
+
   end process comb_proc;
   -- Process updating internal registers based on primary clock
-  seq_proc: process(ext_clk_in, rst)
+  seq_proc: process(ext_in_rec.clk, rst)
   begin
     if(rst = '1') then
-      ext_d_in_reg <= (others => '0');
-      ext_d_out_reg <= (others => '0');
-      ext_clk_out <= '0';
-      ext_parity_out <= '1';
-      curr_state <= IDLE;
+      st.ext_in_reg.data <= (others => '0');
+      st.ext_out_reg.data <= (others => '0');
+      st.ext_out_reg.clk <= '0';
+      st.ext_out_reg.parity <= '1';
+      st.curr_state <= IDLE;
 
-    elsif(rising_edge(ext_clk_in)) then
-      ext_clk_out <= not ext_clk_out;
-      ext_d_in_reg <= ext_d_in;
-      ext_d_out_reg <= int_out.payload;
-      ext_parity_out <= ext_next_parity_out; 
-      curr_state <= next_state;
+    elsif(rising_edge(ext_in_rec.clk)) then
+      st.ext_in_reg.data <= ext_in_rec.data;
+      st.ext_in_reg.clk <= ext_in_rec.clk;
+      st.ext_in_reg.parity <= ext_in_rec.parity;
+      st.ext_out_reg.data <= int_out.payload;
+      st.ext_out_reg.clk <= not st.ext_out_reg.clk;
+      st.ext_out_reg.parity <= next_parity_out; 
+      st.curr_state <= next_state;
     end if; 
   end process seq_proc;
 

src/socbridge_driver_tb.vhd

@@ -33,7 +33,7 @@ architecture tb of socbridge_driver_tb is
     );
   end component socbridge_driver;
   signal clk : std_logic := '0';
-  signal rst : std_logic := '0';
+  signal rst : std_logic;
   signal ext_in  :  ext_socbridge_in_t;
   signal ext_out :  ext_socbridge_out_t;
   signal int_in  :  int_socbridge_in_t;
@@ -57,12 +57,11 @@ begin
       int_out => int_out
   );
 
+  ext_in.control(1) <= clk;
   real_clk_proc: process
   begin
-    clk <= '0';
     for x in 0 to SIMULATION_CYCLE_COUNT*2 loop
       clk <= not clk;
-      ext_in.control(1) <= clk;
       wait for CLK_PERIOD / 2;
     end loop;
     wait;
@@ -105,9 +104,11 @@ begin
   external_stimulus: process
   begin
     rst <= '1';
+    curr_word <= "00000000"; 
     wait for 3 * CLK_PERIOD;
     rst <= '0';
-    curr_word <= "00000000"; 
+    wait for CLK_PERIOD / 2;
+    -- stimulus goes here
     wait for CLK_PERIOD*10;
     wait;
   end process external_stimulus;
@@ -115,22 +116,23 @@ begin
 
   internal_stimulus: process
   begin
+    int_out.is_full_in <= '0';
+    int_out.write_enable_out <= '0';
     wait for 3 * CLK_PERIOD;
-    wait for CLK_PERIOD / 2;
+    -- stimulus goes here
+    int_out.write_enable_out <= '1';
     int_out.payload <= "00000000";
-    wait for CLK_PERIOD;
-    int_out.payload <= "00000001";
-    wait for CLK_PERIOD;
-    int_out.payload <= "00000011";
-    wait for CLK_PERIOD;
-    int_out.payload <= "00000111";
-    wait for CLK_PERIOD;
-    int_out.payload <= "00001111";
-    wait for CLK_PERIOD;
-    int_out.payload <= "00011111";
-    wait for CLK_PERIOD;
-    int_out.payload <= "00111111";
-    wait for CLK_PERIOD;
+    wait until int_in.is_full_out = '0';
+    int_out.payload <= "00000010";
+    wait until int_in.is_full_out = '0';
+    int_out.payload <= "00000100";
+    wait until int_in.is_full_out = '0';
+    int_out.payload <= "00001000";
+    wait until int_in.is_full_out = '0';
+    int_out.payload <= "00010000";
+    wait until int_in.is_full_out = '0';
+    int_out.payload <= "00100000";
+    wait until int_in.is_full_out = '0';
     wait;
   end process internal_stimulus;