fixed a timing issue in buffer

src/fifo_buffer/fifo_buffer.vhd

@@ -53,7 +53,8 @@ begin
   techmap_ram_inst : entity techmap.syncram_2p
   generic map(tech => tech, 
               abits => address_bits, 
-              dbits => fifo_width
+              dbits => fifo_width,
+              sepclk => 1
              )
   port map(
     rclk     => out_clk,
@@ -97,8 +98,8 @@ begin
     if rising_edge(in_clk) and valid_in = '1' and buffer_full = '0' then
       write_pointer <= std_logic_vector(unsigned(write_pointer) + 1);
     end if;
-    if rising_edge(out_clk) then
-      if ready_in = '1' and buffer_empty = '0' and unsigned(read_pointer) + 1 /= unsigned(write_pointer) then
+    if falling_edge(out_clk) then
+      if ready_in = '1' and buffer_empty = '0' then
         read_pointer <= std_logic_vector(unsigned(read_pointer) + 1);
         valid_out <= '1';
       else

src/socbridge/socbridge_driver.vhd

@@ -57,12 +57,14 @@ begin
 
   comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver, 
                      st, controller_to_socbridge_driver, trans_st,
-                     tx_sent_response, rx_received_response)
+                     tx_sent_response, rx_received_response,
+                     valid_out)
     variable curr_response_bits : std_logic_vector(4 downto 0);
     variable local_next_rx_transaction : transaction_t;
     variable local_next_tx_transaction : transaction_t;
     variable local_next_data_out :  std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
   begin
+    -- DEFAULT VALUES
     -- Helpful Bindings --
     next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver.payload(2 downto 0)));
     curr_response_bits := ext_to_socbridge_driver.payload(7 downto 3); 
@@ -418,6 +420,7 @@ begin
       st.socbridge_driver_to_ext_reg.parity <= next_parity_out; 
       st.curr_tx_state <= next_tx_state;
       st.curr_rx_state <= next_rx_state;
+      valid_out <= '0';
       case st.curr_tx_state is
         when IDLE =>
           st.curr_tx_transaction <= next_tx_transaction;   
@@ -452,8 +455,8 @@ begin
           end if;
         when RX_HEADER => 
         when RX_R_BODY =>
-          socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
           valid_out <= '1';
+          socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
           if st.rx_stage > 0 then
             st.rx_stage <= st.rx_stage - 1;
           end if;