Rough outline of new FSMs probably done. All remaining work is hopefully covered by TODOs

src/socbridge/socbridge_driver.vhd

@@ -99,8 +99,8 @@ begin
 --        /       \                 |                            
 --       V        V                 |                         
 --  TX_HEADER   RX_HEADER           |                        
---       |\     /    |              |                           
---       | V   V     |              |                           
+--       |  \   /    |              |                           
+--       |  V  V     |              |                           
 --       |  ADDR1    |              |                           
 --       |    |      |              |                           
 --       |    V      |              |                           
@@ -127,6 +127,16 @@ begin
   --- Next State Assignment Of RX FSM --- 
     case st.curr_rx_state is
       when IDLE => 
+        if PACKET_TYPE = COMMAND then -- TODO Make this a real type and variable
+          next_rx_state <= CMD;
+        elsif PACKET_TYPE = RESPONSE then
+          next_rx_state <= RX_BODY;
+        else
+          next_rx_state <= IDLE;
+        end if;
+      when CMD =>
+      -- TODO This should be changed to not to check 'st.curr_cmd' but rather
+      -- the command received which may not be the same variable
         if st.curr_cmd = WRITE_ADD then
           next_rx_state <= ADDR1;
         elsif st.curr_cmd = WRITE then
@@ -134,54 +144,63 @@ begin
         elsif st.curr_cmd = READ_ADD then
           next_rx_state <= ADDR1;
         elsif st.curr_cmd = READ then
-          next_rx_state <= RX_RESPONSE;
-        else
-          next_rx_state <= IDLE;
-        end if;
-      when RX_HEADER =>
-      -- The header only takes one word (cycle) to transmit.
-      -- Continue to awaiting response directly afterwards.
-        if st.curr_cmd = READ_ADD then
-          next_rx_state <= ADDR1;
-        else 
-          next_rx_state <= RX_RESPONSE;
-        end if;
-      when RX_RESPONSE =>
-      -- Wait for read response. 
-        if curr_response = READ_RESPONSE then
-          next_rx_state <= RX_BODY;
-        else 
-          next_rx_state <= RX_RESPONSE;
+          next_rx_state <= GEN_ACCESS;
         end if;
+      --when RX_HEADER =>
+      ---- The header only takes one word (cycle) to transmit.
+      ---- Continue to awaiting response directly afterwards.
+      --  if st.curr_cmd = READ_ADD then
+      --    next_rx_state <= ADDR1;
+      --  else 
+      --    next_rx_state <= RX_RESPONSE;
+      --  end if;
+      --when RX_RESPONSE =>
+      ---- Wait for read response.
+      --  if curr_response = READ_RESPONSE then
+      --    next_rx_state <= RX_BODY;
+      --  else
+      --    next_rx_state <= RX_RESPONSE;
+      --  end if;
       when RX_BODY =>
       -- Here we want to stay in RX_BODY for the duration of a packet.
         if st.read_stage = 0 then
           next_rx_state <= IDLE;
-        else 
+        else
           next_rx_state <= RX_BODY;
         end if;
       when ADDR1 =>
-      -- Transmits the entire address and returns to the appropriate 
+      -- Transmits the entire address and returns to the appropriate
         next_rx_state <= ADDR2;
       when ADDR2 =>
         next_rx_state <= ADDR3;
       when ADDR3 =>
         next_rx_state <= ADDR4;
-      when ADDR4 => 
+      when ADDR4 =>
+        -- TODO this should probably not be dependant on state's instruction
         if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then 
           next_rx_state <= PAYLOAD;
-        else 
-          next_rx_state <= RX_RESPONSE;
+        else
+          next_rx_state <= RX_BODY;
         end if;
     end case;
     
   --- Next State Assignment Of TX FSM --- 
     case st.curr_tx_state is
-      when IDLE => 
-        if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then
+      when IDLE =>
+        -- Do we have a command, if so enter command state.
+        if st.curr_cmd = READ_ADD or st.curr_cmd = READ or 
+           st.curr_cmd = WRITE_ADD or st.curr_cmd = WRITE then
           next_tx_state <= TX_HEADER;
-        elsif st.curr_cmd = READ or st.curr_cmd = READ_ADD then
-          next_tx_state <= RX_HEADER;
+        -- Otherwise we are ready to send a response to a read.
+        elsif RESPONSE_READY then -- TODO define RESPONSE_READY
+          next_tx_state <= RESPONSE;
+        else 
+          next_tx_state <= IDLE;
+        end if;
+      when RESPONSE =>
+      -- TODO consider whether this should be moved to TX_BODY
+        if MORE_RESPONSE then
+          next_tx_state <= RESPONSE;
         else
           next_tx_state <= IDLE;
         end if;
@@ -201,6 +220,7 @@ begin
           next_tx_state <= TX_BODY;
         end if;
       when TX_ACK =>
+      -- TODO move this to rx FSM
       -- Wait for write acknowledgement. 
         if curr_response = WRITE_ACK then
           next_tx_state <= IDLE;
@@ -218,7 +238,16 @@ begin
         if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then 
           next_tx_state <= TX_BODY;
         else 
-          next_tx_state <= RX_RESPONSE;
+        -- If it is a read instruction we wait for response.
+        -- TODO separate read from NO_OP and P_ERR
+          next_tx_state <= AWAIT;
+        end if;
+      when AWAIT => 
+        -- Wait for RX FSM to get a response
+        if st.curr_rx_state = RX_BODY and st.read_stage = 0 then
+          next_tx_state <= IDLE;
+        else 
+          next_tx_state <= AWAIT;
         end if;
     end case;
 
@@ -237,7 +266,7 @@ begin
         else
         end if;       
       when TX_HEADER =>
-        if st.curr_cmd = WRITE_ADD then
+        if st.curr_cmd = WRITE_ADD or st.curr_cmd = READ_ADD then
           socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
         else 
           socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;

src/socbridge/socbridge_driver_tb_pkg.vhd

@@ -16,13 +16,13 @@ package socbridge_driver_tb_pkg is
     (NO_OP, WRITE_ACK, READ_RESPONSE);
 
   type rx_state_t is
-    (IDLE, RESP, ADDR1, ADDR2, ADDR3, ADDR4, 
-     CMD, READ, WRITE, PAYLOAD,
+    (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, 
+     CMD, RESPONSE, READ, WRITE, PAYLOAD,
      RX_HEADER, RX_RESPONSE, RX_BODY);
 
   type tx_state_t is
-    (IDLE, RESP, ADDR1, ADDR2, ADDR3, ADDR4,
-    CMD, READ, WRITE, PAYLOAD,
+    (IDLE, ADDR1, ADDR2, ADDR3, ADDR4,
+    CMD, RESPONSE, READ, WRITE, PAYLOAD, AWAIT,
      TX_HEADER, TX_BODY, TX_ACK);
   --- TRANSLATOR ---
   type translator_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);