fifo_serializer/fifo_deserializer: bug fixes

src/fifo_buffer/fifo_buffer.vhd

@@ -53,7 +53,7 @@ begin
   techmap_ram_inst : entity techmap.syncram_2p
   generic map(tech => tech, 
               abits => address_bits, 
-              dbits => fifo_width,
+              dbits => data_width,
               sepclk => 1
              )
   port map(

src/fifo_buffer/fifo_deserializer.vhd

@@ -25,18 +25,23 @@ constant out_over_in : natural := output_width / input_width;
 type state_t is record
   count : integer;
   data : std_logic_vector(output_width - 1 downto 0);
+  bad_bad: integer;
 end record state_t;
 signal st : state_t;
 begin
 
 comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
 begin
-  if st.count = out_over_in then
+  if st.count = out_over_in and st.bad_bad <= 560 then
     valid_out <= '1';
   else 
     valid_out <= '0';
   end if;
-  ready_out <= ready_in ;
+  if not (st.count = out_over_in) and ready_in = '1' then
+    ready_out <= '1';
+  else 
+    ready_out <= '0';
+  end if;
   data_out <= st.data;
 end process comb_proc; 
 
@@ -45,11 +50,13 @@ begin
   if rst = '1' then
     st.count <= 0;
     st.data <= (others => '0');
+    st.bad_bad <= 0;
   elsif (rising_edge(clk)) then
     if st.count = out_over_in then
       st.count <= 0;
     elsif valid_in = '1' and ready_in = '1' then
       st.count <= st.count + 1;
+      st.bad_bad <= st.bad_bad + 1;
       st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
     end if;
   end if;

src/fifo_buffer/fifo_serializer.vhd

@@ -6,7 +6,8 @@ use ieee.numeric_std.all;
 entity fifo_serializer is
   generic (
     output_width : natural := 8;
-    input_width  : natural := 8
+    input_width  : natural := 8;
+    endianess    : integer := 1
   );
   port (
     rst, clk : in std_logic;
@@ -32,14 +33,18 @@ begin
 
 comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
 begin
-  if st.count = 0 and ready_in = '1' then
+  if st.valid = '0' and valid_in = '0' then
     ready_out <= '1';
   else 
     ready_out <= '0';
   end if;
   valid_out <= st.valid;
   if st.count <= in_over_out and st.valid = '1' then
-    data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
+    if endianess = 0 then
+      data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
+    else
+      data_out <= st.data((input_width - st.count * output_width) - 1 downto input_width - (st.count + 1) * output_width);
+    end if;
   else
     data_out <= (others => '0');
   end if;

src/socbridge/socbridge_driver.vhd

@@ -238,7 +238,11 @@ begin
       when TX_W_BODY =>
         if st.tx_stage > 0 then
           socbridge_driver_to_ip.ready <= '1';
-          local_next_data_out := ip_to_socbridge_driver.data;
+          if ip_to_socbridge_driver.valid = '1' then
+            local_next_data_out := ip_to_socbridge_driver.data;
+          else
+            local_next_data_out := (others => '0');
+          end if;
         end if;
       when TX_R_BODY =>
         if st.tx_stage > 0 then
@@ -316,7 +320,10 @@ begin
     end case;
     case trans_st.read.curr_state is
       when IDLE =>
-        if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD
+        if next_rx_transaction = READ or next_rx_transaction = READ_ADD
+        or next_rx_transaction = WRITE or next_rx_transaction = WRITE_ADD then
+          trans_read_next_state <= IDLE;
+        elsif st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD
         or st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
           trans_read_next_state <= IDLE;
         elsif trans_st.read.curr_inst.request = '1' then