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base: kryddan:cd6ff9a77a43d723550df08a11b4da9234c3fb20
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kryddan:main
kryddan:ganimede-space-optimized
kryddan:ganimede-single-issue
kryddan:ganimede-multipacket
kryddan:ganimede-rework
kryddan:management-unit
kryddan:ganimede
kryddan:scripts
kryddan:admin
kryddan:v1.0.0
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compare: kryddan:5f9783f3b3e477eb9448190fbbb12f502b1e7fed
Branches Tags
kryddan:ganimede-space-optimized
kryddan:ganimede-single-issue
kryddan:ganimede-multipacket
kryddan:ganimede-rework
kryddan:management-unit
kryddan:ganimede
kryddan:scripts
kryddan:admin
kryddan:main
kryddan:v1.0.0

2 Commits
cd6ff9a77a ... 5f9783f3b3

Author SHA1 Message Date
Erik Örtenberg
5f9783f3b3 cleanup: removed instruction type from translator (not used, and currently implied by which translator it is) 2025-05-23 15:42:50 +02:00
Erik Örtenberg
09a5318523 cleanup: made manager address be kept in one variable (io pipelined access to ganimede isn't likely) 2025-05-23 15:35:41 +02:00
2 changed files with 32 additions and 27 deletions
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47
src/socbridge/socbridge_driver.vhd
View File

@ -287,17 +287,17 @@ begin
when RX_W_BODY =>
if st.rx_stage mod 4 = 0 and st.rx_stage /= st.rx_data_size then
socbridge_driver_to_manager.data <= st.curr_write_data;
socbridge_driver_to_manager.address <= st.curr_rx_write_addr;
socbridge_driver_to_manager.address <= st.manager_addr;
socbridge_driver_to_manager.valid <= '1';
end if;
when RX_R_BODY =>
when RX_AWAIT =>
if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
socbridge_driver_to_manager.data <= st.curr_write_data;
socbridge_driver_to_manager.address <= st.curr_rx_write_addr;
socbridge_driver_to_manager.address <= st.manager_addr;
socbridge_driver_to_manager.valid <= '1';
else
socbridge_driver_to_manager.address <= st.curr_rx_read_addr;
socbridge_driver_to_manager.address <= st.manager_addr;
end if;
when ADDR1 =>
when ADDR2 =>
@ -438,8 +438,7 @@ begin
st.curr_rx_transaction <= NO_OP;
st.tx_data_size <= 0;
st.rx_data_size <= 0;
st.curr_rx_read_addr <= (others => '0');
st.curr_rx_write_addr <= (others => '0');
st.manager_addr <= (others => '0');
st.curr_write_data <= (others => '0');
st.curr_read_data <= (others => '0');
socbridge_driver_to_ip.data <= (others => '0');
@ -450,8 +449,8 @@ begin
elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data;
st.ext_to_socbridge_driver_reg.clk <= ext_to_socbridge_driver_rec.clk;
st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
-- PARITY CHECK NOT IMPLEMENTED, REMOVING
--st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
st.socbridge_driver_to_ext_reg.data <= next_data_out;
st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
st.socbridge_driver_to_ext_reg.parity <= next_parity_out;
@ -558,41 +557,41 @@ begin
st.curr_write_data((((st.rx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.rx_stage - 1) mod 4) + 1) - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
end if;
if (st.rx_stage - 2) mod 4 = 0 and st.rx_data_size - st.rx_stage > 4 then
st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32));
st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
end if;
when RX_AWAIT =>
st.curr_read_data <= manager_to_socbridge_driver.data;
-- THIS DOESN'T WORK FOR LARGER THAN 4 BYTE ACCESSES, SHOULD BE FIXED BUT NOT NEEDED IF ONLY 4 BYTE ACCESSES ARRIVE
if st.curr_tx_transaction = READ_RESPONSE or st.curr_tx_transaction = WRITE_ACK then
if (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then
st.curr_rx_read_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_read_addr) + 4), 32));
st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
elsif (st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD) and (st.rx_stage - 2) mod 4 = 0 then
st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32));
st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
end if;
end if;
when ADDR1 =>
if st.curr_rx_transaction = READ_ADD then
st.curr_rx_read_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
else
st.curr_rx_write_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
end if;
when ADDR2 =>
if st.curr_rx_transaction = READ_ADD then
st.curr_rx_read_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
else
st.curr_rx_write_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
end if;
when ADDR3 =>
if st.curr_rx_transaction = READ_ADD then
st.curr_rx_read_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
else
st.curr_rx_write_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
end if;
when ADDR4 =>
if st.curr_rx_transaction = READ_ADD then
st.curr_rx_read_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
else
st.curr_rx_write_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
end if;
when others =>
end case;
@ -605,13 +604,11 @@ begin
trans_st.read.curr_inst.request <= '0';
trans_st.read.curr_inst.address <= (others => '0');
trans_st.read.curr_inst.seq_mem_access_count <= 0;
trans_st.read.curr_inst.instruction <= NO_OP;
trans_st.read.is_first_word <= '1';
trans_st.write.curr_state <= IDLE;
trans_st.write.curr_inst.request <= '0';
trans_st.write.curr_inst.address <= (others => '0');
trans_st.write.curr_inst.seq_mem_access_count <= 0;
trans_st.write.curr_inst.instruction <= NO_OP;
trans_st.write.is_first_word <= '1';
elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
trans_st.read.curr_state <= trans_read_next_state;
@ -620,7 +617,9 @@ begin
when IDLE =>
if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = WRITE
and trans_st.write.curr_inst.request = '0' then
trans_st.write.curr_inst <= controller_to_socbridge_driver;
trans_st.write.curr_inst.request <= controller_to_socbridge_driver.request;
trans_st.write.curr_inst.address <= controller_to_socbridge_driver.address;
trans_st.write.curr_inst.seq_mem_access_count <= controller_to_socbridge_driver.seq_mem_access_count;
else
end if;
trans_st.write.is_first_word <= '1';
@ -643,7 +642,6 @@ begin
trans_st.write.curr_inst.request <= '0';
trans_st.write.curr_inst.address <= (others => '0');
trans_st.write.curr_inst.seq_mem_access_count <= 0;
trans_st.write.curr_inst.instruction <= NO_OP;
end if;
if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then
trans_st.write.is_first_word <= '1';
@ -658,7 +656,9 @@ begin
case trans_st.read.curr_state is
when IDLE =>
if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = READ then
trans_st.read.curr_inst <= controller_to_socbridge_driver;
trans_st.read.curr_inst.request <= controller_to_socbridge_driver.request;
trans_st.read.curr_inst.address <= controller_to_socbridge_driver.address;
trans_st.read.curr_inst.seq_mem_access_count <= controller_to_socbridge_driver.seq_mem_access_count;
else
end if;
trans_st.read.is_first_word <= '1';
@ -679,7 +679,6 @@ begin
trans_st.read.curr_inst.request <= '0';
trans_st.read.curr_inst.address <= (others => '0');
trans_st.read.curr_inst.seq_mem_access_count <= 0;
trans_st.read.curr_inst.instruction <= NO_OP;
end if;
if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then
trans_st.read.is_first_word <= '1';

12
src/socbridge/socbridge_driver_pkg.vhd
View File

@ -23,8 +23,15 @@ package socbridge_driver_pkg is
--- TRANSLATOR ---
type ctrl_inst_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);
type ctrl_inst_t is record
request : std_logic;
address : std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count : integer;
instruction : instruction_command_t;
end record ctrl_inst_t;
type ctrl_inst_state_rec_t is record
curr_inst : controller_to_socbridge_driver_t;
curr_inst : ctrl_inst_t;
curr_state : ctrl_inst_state_t;
is_first_word : std_logic;
end record ctrl_inst_state_rec_t;
@ -51,8 +58,7 @@ package socbridge_driver_pkg is
curr_write_data : std_logic_vector(31 downto 0);
curr_read_data : std_logic_vector(31 downto 0);
curr_tx_addr : std_logic_vector(31 downto 0);
curr_rx_read_addr : std_logic_vector(31 downto 0);
curr_rx_write_addr : std_logic_vector(31 downto 0);
manager_addr : std_logic_vector(31 downto 0);
read_in_flight : boolean;
write_in_flight : boolean;
last_sent_transaction : transaction_t;