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ganimede-toplevel-template #13

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Adam merged 41 commits from ganimede-toplevel-template into main 2025-03-13 16:41:18 +01:00
Conversation 0 Commits 41 Files Changed 16 +15 -76
2 changed files with 15 additions and 76 deletions
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85
src/control_socbridge_merge/control_socbridge_tb.vhd
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@ -13,7 +13,7 @@ end entity control_socbridge_tb;
architecture tb of control_socbridge_tb is architecture tb of control_socbridge_tb is
constant CLK_PERIOD : Time := 10 ns; constant CLK_PERIOD : Time := 10 ns;
constant SIMULATION_CYCLE_COUNT : integer := 200; constant SIMULATION_CYCLE_COUNT : integer := 2000;
signal clk, rst : std_logic := '0'; signal clk, rst : std_logic := '0';
signal cu_to_sb_cmd: command_t; signal cu_to_sb_cmd: command_t;
signal cu_to_sb_address: std_logic_vector(31 downto 0); signal cu_to_sb_address: std_logic_vector(31 downto 0);
@ -125,7 +125,7 @@ begin
ext_control_input.address <= (others => '0'); ext_control_input.address <= (others => '0');
ext_control_input.cmd <= "00"; ext_control_input.cmd <= "00";
ext_control_input.driver_id <= "1"; ext_control_input.driver_id <= "1";
ext_control_input.seq_mem_access_count <= 2; ext_control_input.seq_mem_access_count <= 256;
wait for 3 * CLK_PERIOD; wait for 3 * CLK_PERIOD;
report "Reset grace period ended, starting stimulus..."; report "Reset grace period ended, starting stimulus...";
rst <= '0'; rst <= '0';
@ -137,6 +137,7 @@ begin
ext_control_input.cmd <= "00"; ext_control_input.cmd <= "00";
wait until int_control_input.active_driver(0) = '0'; wait until int_control_input.active_driver(0) = '0';
wait for CLK_PERIOD; wait for CLK_PERIOD;
ext_control_input.seq_mem_access_count <= 2;
report "Task completed in driver, sending next task..."; report "Task completed in driver, sending next task...";
ext_control_input.address <= x"FA0FA0FA"; ext_control_input.address <= x"FA0FA0FA";
ext_control_input.cmd <= "10"; ext_control_input.cmd <= "10";
@ -169,10 +170,12 @@ begin
curr_word <= "00001001"; curr_word <= "00001001";
wait for CLK_PERIOD; wait for CLK_PERIOD;
curr_word <= "00000000"; curr_word <= "00000000";
wait for CLK_PERIOD * 20; wait for CLK_PERIOD * 140;
curr_word <= "00101001"; curr_word <= "00101001";
wait for CLK_PERIOD; wait for CLK_PERIOD;
curr_word <= "00000000"; curr_word <= "00000000";
wait for CLK_PERIOD * 140;
curr_word <= "00101001";
wait for CLK_PERIOD*20; wait for CLK_PERIOD*20;
curr_word <= "01100001"; curr_word <= "01100001";
wait for CLK_PERIOD; wait for CLK_PERIOD;
@ -198,76 +201,12 @@ begin
input := input + 1 mod 256; input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk); wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1'; for x in 0 to 1000 loop
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length)); int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256; input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0'; wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk); wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1'; end loop;
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
int_socbridge_in.write_enable_out <= '1';
int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
input := input + 1 mod 256;
wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
wait until falling_edge(clk);
wait; wait;
end process internal_stimulus; end process internal_stimulus;

6
src/socbridge/socbridge_driver.vhd
View File

@ -300,8 +300,8 @@ begin
end if; end if;
end if; end if;
if trans_st.curr_inst.seq_mem_access_count > 256 then if trans_st.curr_inst.seq_mem_access_count > 128 then
next_cmd_size <= 256; next_cmd_size <= 128;
elsif trans_st.curr_inst.seq_mem_access_count > 0 then elsif trans_st.curr_inst.seq_mem_access_count > 0 then
next_cmd_size <= trans_st.curr_inst.seq_mem_access_count; next_cmd_size <= trans_st.curr_inst.seq_mem_access_count;
else else
@ -384,7 +384,7 @@ begin
trans_st.is_first_word <= '1'; trans_st.is_first_word <= '1';
when SEND => when SEND =>
when SEND_ACCEPTED => when SEND_ACCEPTED =>
trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - 256; trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - 128;
when AWAIT => when AWAIT =>
if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_state = IDLE then if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_state = IDLE then
trans_st.curr_inst.request <= '0'; trans_st.curr_inst.request <= '0';