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management-unit #18

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Adam wants to merge 5 commits from management-unit into ganimede-rework
pull from: management-unit
merge into: kryddan:ganimede-rework
Conversation 0 Commits 5 Files Changed 11 +26 -26
4 changed files with 26 additions and 26 deletions
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Showing only changes of commit 15cc7c6000 - Show all commits

16
src/controller/control_unit.vhd
View File

@ -8,8 +8,8 @@ entity control_unit is
port (
clk, rst : in std_logic;
cpu_to_controller : in cpu_to_controller_t;
controller_to_cpu : out controller_to_cpu_t;
manager_to_controller : in manager_to_controller_t;
controller_to_manager : out controller_to_manager_t;
drivers_to_controller : in drivers_to_controller_t;
controller_to_drivers : out controller_to_drivers_t
);
@ -31,7 +31,7 @@ architecture behave of control_unit is
begin
comb_proc: process(cpu_to_controller, drivers_to_controller, state)
comb_proc: process(manager_to_controller, drivers_to_controller, state)
begin
ored := '0';
ready_reduction: for i in 0 to number_of_drivers - 1 loop
@ -40,7 +40,7 @@ begin
controller_to_drivers.socbridge.request <= state.curr_driver;
controller_to_drivers.socbridge.address <= state.address;
controller_to_drivers.socbridge.seq_mem_access_count <= state.seq_mem_access_count;
controller_to_cpu.ready <= state.ready;
controller_to_manager.ready <= state.ready;
controller_to_drivers.socbridge.instruction <= state.instruction;
end process comb_proc;
@ -56,10 +56,10 @@ begin
else
state.ready <= not ored;
if ored = '0' then
state.address <= cpu_to_controller.address;
state.seq_mem_access_count <= cpu_to_controller.seq_mem_access_count;
state.curr_driver <= cpu_to_controller.driver_id(0);
with cpu_to_controller.cmd select
state.address <= manager_to_controller.address;
state.seq_mem_access_count <= manager_to_controller.seq_mem_access_count;
state.curr_driver <= manager_to_controller.driver_id(0);
with manager_to_controller.cmd select
state.instruction <= WRITE when "01",
READ when "10",
NO_OP when others;

16
src/controller/control_unit_tb.vhd
View File

@ -14,13 +14,13 @@ architecture tb of control_unit_tb is
constant cycle: Time := 10 ns;
signal clock: std_logic := '0';
signal reset: std_logic := '0';
signal cpu_to_controller: cpu_to_controller_t := (
signal manager_to_controller: manager_to_controller_t := (
(others => '0'),
(others => '0'),
0,
"00");
signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0'));
signal controller_to_cpu: controller_to_cpu_t;
signal controller_to_manager: controller_to_manager_t;
signal controller_to_drivers: controller_to_drivers_t;
signal current_driver : std_logic_vector(0 downto 0) := "0";
shared variable word_counter: natural := 0;
@ -40,8 +40,8 @@ begin
port map(
clk => clock,
rst => reset,
cpu_to_controller => cpu_to_controller,
controller_to_cpu => controller_to_cpu,
manager_to_controller => manager_to_controller,
controller_to_manager => controller_to_manager,
drivers_to_controller => drivers_to_controller,
controller_to_drivers => controller_to_drivers
);
@ -50,11 +50,11 @@ stimulus_proc: process
begin
wait for cycle;
cpu_to_controller.driver_id <= "1";
manager_to_controller.driver_id <= "1";
drivers_to_controller.socbridge.is_active <= '0';
cpu_to_controller.address <= x"F0F0F0F0";
cpu_to_controller.seq_mem_access_count <= 3;
cpu_to_controller.cmd <= "01";
manager_to_controller.address <= x"F0F0F0F0";
manager_to_controller.seq_mem_access_count <= 3;
manager_to_controller.cmd <= "01";
word_counter := 3;
wait for cycle;
current_driver <= "1";

10
src/ganimede/ganimede.vhd
View File

@ -10,8 +10,8 @@ entity ganimede_toplevel is
port (
clk : in std_logic;
rst : in std_logic;
cpu_to_ganimede : in cpu_to_controller_t;
ganimede_to_cpu : out controller_to_cpu_t;
manager_to_ganimede : in manager_to_controller_t;
ganimede_to_manager : out controller_to_manager_t;
ext_to_ganimede : in ext_to_ganimede_t;
ganimede_to_ext : out ganimede_to_ext_t;
ip_to_ganimede : in ip_to_ganimede_t;
@ -54,7 +54,7 @@ begin
ganimede_to_ext <= drivers_to_ext;
--- DRIVER INSTANTIATION ---
socbridge_inst: entity socbridge.socbridge_driver
socbridge_inst: entity gan_socbridge.socbridge_driver
port map(
clk => clk,
rst => rst,
@ -70,8 +70,8 @@ begin
port map(
clk => clk,
rst => rst,
cpu_to_controller => cpu_to_ganimede,
controller_to_cpu => ganimede_to_cpu,
manager_to_controller => manager_to_ganimede,
controller_to_manager => ganimede_to_manager,
drivers_to_controller => drivers_to_controller,
controller_to_drivers => controller_to_drivers
);

10
src/ganimede/io_type_pkg.vhd
View File

@ -23,16 +23,16 @@ package io_types is
end record interface_inst_t;
--- CONTROL UNIT ---
type cpu_to_controller_t is record
type manager_to_controller_t is record
driver_id : std_logic_vector(number_of_drivers - 1 downto 0);
address : std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count : integer;
cmd : std_logic_vector(1 downto 0);
end record cpu_to_controller_t;
cmd : std_logic_vector(1 downto 0); --Noop: 00; Write: 01; Read: 10
end record manager_to_controller_t;
type controller_to_cpu_t is record
type controller_to_manager_t is record
ready : std_logic;
end record controller_to_cpu_t;
end record controller_to_manager_t;
--- PROTOCOL INFORMATION ---
constant interface_inst : interface_inst_t := (