src/ganimede/ganimede_tb.vhd

@@ -3,8 +3,8 @@ use IEEE.std_logic_1164.all;
 use IEEE.NUMERIC_STD.all;
 library ganimede;
 use ganimede.io_types.all;
-library socbridge;
+library gan_socbridge;
-use socbridge.socbridge_driver_tb_pkg.all;
+use gan_socbridge.socbridge_driver_tb_pkg.all;
 library controller;
 
 entity ganimede_tb is

src/gantry.toml

@@ -4,7 +4,7 @@ maintainer = ""
 email = ""
 version = "0.0.1"
 
-[libraries.socbridge]
+[libraries.gan_socbridge]
 vhdl-version = "93c"
 path = "socbridge"
 
@@ -183,3 +183,7 @@ path = "grlib-com-nx-2024.4-b4295/lib/micron"
 [libraries.ahb2ahb]
 vhdl-version = "93c"
 path = "grlib-com-nx-2024.4-b4295/verification/ahb2ahb"
+
+[libraries.manager]
+vhdl-version = "93c"
+path = "manager"

src/manager/management_unit.vhd

@@ -52,13 +52,13 @@ begin
       end if;
 
       -- Is there a read instruction in memory
-      if read_address /= (others => '0') and controller_to_manager.ready = '1' then
+      if read_address /= empty_word and controller_to_manager.ready = '1' then
         manager_to_controller.address <= read_address;
         manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
         manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size));
         manager_to_controller.cmd <= "10";
       -- Is there a write instruction in memory
-      elsif write_address /= (others => '0') and controller_to_manager.ready = '1' then
+      elsif write_address /= empty_word and controller_to_manager.ready = '1' then
         manager_to_controller.address <= write_address;
         manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
         manager_to_controller.seq_mem_access_count <= to_integer(unsigned(msg_size));

src/manager/management_unit_pkg.vhd

@@ -7,16 +7,17 @@ use ganimede.io_types.all;
 package management_types is
   constant WORD_SIZE : natural := 32;
   subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0);
+  constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
   constant mem_words : natural := 64;
   type memory_t is array (0 to mem_words - 1) of manager_word_t;
 
   -- Index in memory array where memory read address is kept.
   -- Read is active while it is not all zero.
-  constant read_address_index  : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
+  constant read_address_index  : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000000";
   -- Index in memory array where memory write address is kept.
   -- Write is active while it is not all zero. Mutex with read address
-  constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0') & '1';
+  constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000001";
-  constant access_size         : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0') & "10";
+  constant access_size         : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000010";
 
   -- Status register for debugging
   type manager_state_t is record
@@ -25,7 +26,7 @@ package management_types is
   end record manager_state_t;
 
   -- reset value of status register
-  constant manager_state_reset_val : manager_state_t := ((others => (others => '0')), x"0000");
+  constant manager_state_reset_val : manager_state_t := ((others => (others => '0')), x"00000000");
 
   type socbridge_driver_to_manager_t is record
     address : manager_word_t;

src/manager/management_unit_tb.vhd

@@ -0,0 +1,118 @@
+library IEEE;  
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use IEEE.numeric_std.all;
+library ganimede;
+use ganimede.io_types.all;
+library manager;
+use manager.management_types.all;
+
+entity management_unit_tb is
+end entity management_unit_tb;
+
+architecture tb of management_unit_tb is
+  signal clk : std_logic := '0';
+  signal rst : std_logic;
+  
+  signal manager_to_controller       : manager_to_controller_t;       
+  signal controller_to_manager       : controller_to_manager_t := (ready => '0'); 
+  signal socbridge_driver_to_manager : socbridge_driver_to_manager_t := (
+    address => (others => '0'),
+    data => (others => '0'),
+    valid => '0'
+  );
+  signal manager_to_socbridge_driver : manager_to_socbridge_driver_t; 
+
+  constant halfcycle: Time := 5 ns;
+  constant cycle: Time := 2 * halfcycle;
+
+  function to_string ( a: std_logic_vector) return string is
+  variable b : string (1 to a'length) := (others => NUL);
+  variable stri : integer := 1; 
+  begin
+      for i in a'range loop
+          b(stri) := std_logic'image(a((i)))(2);
+      stri := stri+1;
+      end loop;
+  return b;
+  end function;
+
+begin
+  
+  clock_proc: process
+  begin
+  for i in 0 to 50 loop
+    wait for halfcycle;
+    clk <= not clk;
+  end loop;
+  wait;
+  end process clock_proc;
+
+  management_unit_inst: entity manager.management_unit
+    port map(
+    clk             => clk,
+    rst             => rst,
+    manager_to_controller       => manager_to_controller,
+    controller_to_manager       => controller_to_manager, 
+    socbridge_driver_to_manager => socbridge_driver_to_manager,
+    manager_to_socbridge_driver => manager_to_socbridge_driver 
+    );
+  
+tb_proc: process
+begin
+  controller_to_manager.ready <= '0'; 
+  rst <= '1';
+  wait for cycle;
+  rst <= '0';
+
+  wait for 5 * cycle;
+
+  report "Testing write to 0x00000005\n";
+  socbridge_driver_to_manager.data <= x"FA0FA0FA";
+  socbridge_driver_to_manager.address <= x"00000005";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.valid <= '0';
+  socbridge_driver_to_manager.data <= x"00000000";
+  assert manager_to_socbridge_driver.data = x"FA0FA0FA" report "Write to address 0x00000005 failed! expected 0xFA0FA0FA but got " & to_string(manager_to_socbridge_driver.data) & "\n" severity error;
+
+  wait for 5 * cycle;
+
+  report "Testing submission of write instruction of 10 words to address 0x40000000\n";
+  socbridge_driver_to_manager.data <= x"40000000";
+  socbridge_driver_to_manager.address <= x"00000001";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.data <= x"0000000A";
+  socbridge_driver_to_manager.address <= x"00000002";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.valid <= '0';
+  socbridge_driver_to_manager.data <= x"00000000";
+  controller_to_manager.ready <= '1';
+  assert manager_to_controller.address = x"40000000" report "Controller got the wrong address! Expected 0x40000000 but got" & to_string(manager_to_controller.address) & "\n" severity error;
+  assert manager_to_controller.cmd = "10" report "Controller got the wrong command! Expected 0b10 but got " & to_string(manager_to_controller.cmd) & "\n" severity error;  
+  assert manager_to_controller.seq_mem_access_count = 10 report "Controller got the wrong message size! expected 10 but got " & natural'image(manager_to_controller.seq_mem_access_count) & "\n" severity error;  
+
+  wait for 5 * cycle;
+  controller_to_manager.ready <= '0'; 
+
+  report "Testing submission of read instruction of 20 words from address 0x50000000\n";
+  socbridge_driver_to_manager.data <= x"50000000";
+  socbridge_driver_to_manager.address <= x"00000000";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.data <= x"00000014";
+  socbridge_driver_to_manager.address <= x"00000002";
+  socbridge_driver_to_manager.valid <= '1';
+  wait for cycle;
+  socbridge_driver_to_manager.valid <= '0';
+  socbridge_driver_to_manager.data <= x"00000000";
+  controller_to_manager.ready <= '1';
+  assert manager_to_controller.address = x"50000000" report "Controller got the wrong address! Expected 0x50000000 but got" & to_string(manager_to_controller.address) & "\n" severity error;
+  assert manager_to_controller.cmd = "01" report "Controller got the wrong command! Expected 0b01 but got " & to_string(manager_to_controller.cmd) & "\n" severity error;  
+  assert manager_to_controller.seq_mem_access_count = 20 report "Controller got the wrong message size! expected 20 but got " & natural'image(manager_to_controller.seq_mem_access_count) & "\n" severity error;  
+  wait;
+end process tb_proc;
+  
+end architecture tb ;

src/socbridge/socbridge_driver_tb.gtkw

@@ -1,77 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Thu Feb 27 10:27:13 2025
-[*]
-[dumpfile] "/home/thesis1/repos/exjobb-public/src/wave/socbridge_driver_tb-tb.ghw"
-[dumpfile_mtime] "Thu Feb 27 10:26:19 2025"
-[dumpfile_size] 2417
-[savefile] "/home/thesis1/repos/exjobb-public/src/socbridge_driver_tb.gtkw"
-[timestart] 21800000
-[size] 956 1033
-[pos] -1 -1
-*-24.456779 22000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] top.
-[treeopen] top.socbridge_driver_tb.
-[treeopen] top.socbridge_driver_tb_pkg.
-[treeopen] top.socbridge_driver_tb_pkg.g_st.
-[sst_width] 273
-[signals_width] 214
-[sst_expanded] 1
-[sst_vpaned_height] 324
-@800200
--Outwards
--Internal
-@28
-top.socbridge_driver_tb.int_out.is_full_in
-@22
-#{top.socbridge_driver_tb.int_out.payload[7:0]} top.socbridge_driver_tb.int_out.payload[7] top.socbridge_driver_tb.int_out.payload[6] top.socbridge_driver_tb.int_out.payload[5] top.socbridge_driver_tb.int_out.payload[4] top.socbridge_driver_tb.int_out.payload[3] top.socbridge_driver_tb.int_out.payload[2] top.socbridge_driver_tb.int_out.payload[1] top.socbridge_driver_tb.int_out.payload[0]
-@28
-top.socbridge_driver_tb.int_out.write_enable_out
-@1000200
--Internal
-@800200
--External
-@28
-+{clk} top.socbridge_driver_tb.ext_out.control[1]
-+{parity} top.socbridge_driver_tb.ext_out.control[0]
-+{next_parity} top.socbridge_driver_tb_pkg.g_next_parity_out
-@22
-#{top.socbridge_driver_tb.ext_out.payload[7:0]} top.socbridge_driver_tb.ext_out.payload[7] top.socbridge_driver_tb.ext_out.payload[6] top.socbridge_driver_tb.ext_out.payload[5] top.socbridge_driver_tb.ext_out.payload[4] top.socbridge_driver_tb.ext_out.payload[3] top.socbridge_driver_tb.ext_out.payload[2] top.socbridge_driver_tb.ext_out.payload[1] top.socbridge_driver_tb.ext_out.payload[0]
-+{next_payload[7:0]} #{top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[7:0]} top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[7] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[6] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[5] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[4] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[3] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[2] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[1] top.socbridge_driver_tb_pkg.g_ext_out_data_cmd[0]
-@1000200
--External
--Outwards
-@800200
--Inwards
--Internal
-@28
-top.socbridge_driver_tb.int_in.is_full_out
-@22
-#{top.socbridge_driver_tb.int_in.payload[7:0]} top.socbridge_driver_tb.int_in.payload[7] top.socbridge_driver_tb.int_in.payload[6] top.socbridge_driver_tb.int_in.payload[5] top.socbridge_driver_tb.int_in.payload[4] top.socbridge_driver_tb.int_in.payload[3] top.socbridge_driver_tb.int_in.payload[2] top.socbridge_driver_tb.int_in.payload[1] top.socbridge_driver_tb.int_in.payload[0]
-@28
-top.socbridge_driver_tb.int_in.write_enable_in
-@1000200
--Internal
-@800200
--External
-@28
-+{clk} top.socbridge_driver_tb.ext_in.control[1]
-+{parity} top.socbridge_driver_tb.ext_in.control[0]
-@22
-#{top.socbridge_driver_tb.ext_in.payload[7:0]} top.socbridge_driver_tb.ext_in.payload[7] top.socbridge_driver_tb.ext_in.payload[6] top.socbridge_driver_tb.ext_in.payload[5] top.socbridge_driver_tb.ext_in.payload[4] top.socbridge_driver_tb.ext_in.payload[3] top.socbridge_driver_tb.ext_in.payload[2] top.socbridge_driver_tb.ext_in.payload[1] top.socbridge_driver_tb.ext_in.payload[0]
-@1000200
--External
--Inwards
-@800200
--Internal Signals
-@420
-top.socbridge_driver_tb_pkg.g_st.curr_state
-+{next_state} top.socbridge_driver_tb_pkg.g_next_state
-top.socbridge_driver_tb_pkg.g_curr_command
-top.socbridge_driver_tb_pkg.g_curr_respoonse
-@1000200
--Internal Signals
-@420
-top.socbridge_driver_tb.cmd
-[pattern_trace] 1
-[pattern_trace] 0

src/socbridge/socbridge_driver_tb.vhd

@@ -5,7 +5,7 @@ library work;
 use work.socbridge_driver_tb_pkg.all;
 library ganimede;
 use ganimede.io_types.all;
-library socbridge;
+library gan_socbridge;
 
 
 entity socbridge_driver_tb is

src/vhdl_ls.toml

@@ -13,6 +13,9 @@ gan_socbridge.files = [
 controller.files = [
     'controller/*.vhd',
 ]
+manager.files = [
+    'manager/*.vhd',
+]
 grlib.files = [
    'grlib-com-nx-2024.4-b4295/lib/grlib/**/*.vhd',
 ]